Computer Architecture Comprehensive Exam at Stanford University, Exams of Computer Architecture and Organization

Download Computer Architecture Comprehensive Exam at Stanford University and more Exams Computer Architecture and Organization in PDF only on Docsity! Stanford University 2007 Computer Architecture Comprehensive Exam Exam Instructions Answer each of the questions included in the exam. Write all of your answers directly on the examination paper, including any work that you wish to be considered for partial credit. The examination is open-book, and you may make use of the text, handouts, your own course notes, and a calculator. On equations: Wherever possible, make sure to include the equation, the equation rewritten with the numerical values, and the final solution. Partial credit will be weighted appropriately for each component of the problem, and providing more information improves the likelihood that partial credit can be awarded. On writing code: Unless otherwise stated, you are free to use any of the assembly instructions listed in the Appendix at the back of the book, including pseudoinstructions. You do not need to optimize your MIPS code unless specifically instructed to do so. On time: You will have one hour to complete this exam. Budget your time and try to leave some time at the end to go over your work. The point weightings correspond roughly to the time each problem is expected to take. THE STANFORD UNIVERSITY HONOR CODE The Honor Code is an undertaking of the students, individually and collectively: 1. that they will not give or receive aid in examinations; that they will not give or receive unpermitted aid in class work, in the preparation of reports, or in any other work that is to be used by the instructor as the basis of grading; 2. that they will do their share and take an active part in seeing to it that others as well as themselves uphold the spirit and letter of the Honor Code. I acknowledge and accept the Honor Code. Magic Number: Score Grader 1. Short Answer (15) 2. Pipelining (15) 3. Memory Heirarchy (15) 4. Cache Math (5) 5. MIPS Assembly (10) TOTAL (60) - 1 of 10 - Problem 1: Short Answer (15 points) Please provide short, concise answers. (1) (2 points) Your company, Acme Corp., is deciding between two computer systems to deploy its new killer Road Runner Tracking application. Ben Bitdiddle says that his company’s system has the better performance because it has the higher clock speed and the higher IPC. Explain why his logic is flawed. (2) (2 points) Some RISC architectures require the compiler (or assembly programmer) to guarantee that a register not be accessed for a given number of cycles after it is loaded from memory. Give an advantage and a disadvantage of this design choice. (3) (2 points) Ben Bitdiddle is writing an optimizing compiler for an architecture that supports virtual memory. He notices that his target processor can execute an unaligned 32 bit load more quickly than an 8 bit load. Is it okay for his compiler to emit 32 bit loads and then ignore the extra 24 bits? Why or why not? (4) (3 points) Briefly describe the data access pattern of an application for which an LRU (least recently used) cache replacement policy performs worse than a random replacement policy. - 2 of 10 - 5 3 1 3 4 2 5 2 1 5 3 1 3 4 2 5 2 1 5 3 1 3 4 2 5 2 1 5 3 1 3 4 2 5 2 1 5 3 1 3 4 2 5 2 1 5 3 1 3 4 2 5 2 1 (These diagrams are for scratch work; no solution written here will be graded. Record your solution on the previous page.) - 5 of 10 - Problem 3: Memory Heirarchy (15 points) Assume you have a 1 GHz processor with 2-levels of cache and DRAM main memory. The first level cache is split for instructions and data. The system does not use early restart or critical word first, i.e. data blocks must be completely transfered before their results are available. The memory system has the following parameters (Note that here 1KB = 1024 bytes): Hit Time Miss Rate Block Size Level-1 cache 1 cycle 6% for data 32 bytes 2% for instruction Level-2 cache 12 cycles + (1 cycle per 64 bits) 2% 256 bytes DRAM 70ns + (10ns per 8 bytes) – – The system includes a TLB with a miss rate of 0.5% for data and never incurs a TLB miss for instructions. The TLB miss penalty is 300 cycles and TLB hits take place in parallel with level-1 cache access. All caches in the system are virtually indexed and physically tagged. Assume that the system never swaps memory out to disk. (1) (5 points) What is the average memory access time (AMAT) in clock cycles for instructions? - 6 of 10 - (2) (5 points) What is the AMAT in clock cycles for data? Assume all data accesses are loads. - 7 of 10 -