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Memory Hierarchy and Cache Systems: Concepts and Performance Analysis, Exams of Computer Architecture and Organization

Various aspects of memory hierarchy and cache systems, including false sharing, clustering, cache coherence, victim cache, interleaved memory, shared memory, message passing machines, and cache associativity. It also includes questions and answers on cache hit time, prefetching, inclusion property, and disk transfer times.

Typology: Exams

Pre 2010

Uploaded on 07/30/2009

koofers-user-rh8
koofers-user-rh8 🇺🇸

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Download Memory Hierarchy and Cache Systems: Concepts and Performance Analysis and more Exams Computer Architecture and Organization in PDF only on Docsity! 1. True or False: (1) Semiconductor memory will not replace magnetic disks in desktop and server computer systems in the near future. (1) Computer systems achieve 99.999% availability ("five nines"), as advertised. (1) Computer components fail suddenly, with little warning. (1) Amdahl’s law applies to parallel computers. (1) You can predict cache performance of Program A by analyzing Program B. (1) Linear speedups are needed to make multiprocessors cost-effective. (1) Scalability is almost free. 2. (3) What is the goal of the memory heirarchy? What two principles make it work? 3. (10) What do the following acronyms stand for: SMT SMP MTTF SRAM COMA ATM RAID DIMM NUMA MPP DSM ROM CMP WAN TLB CD MIMD SIMD DDR SDRAM PCI - 1 - Short Answers: 4. (3) What is false sharing? 5. (3) What is a cluster? 6. (3) What is the difference between connection-oriented and connectionless communication? 7. (3) Give three techniques used to reduce cache hit time. - 2 - 13. (12) Given the following data: Hit time for direct-mapped L2 cache = 10 clock cycles Local miss rate for direct-mapped L2 cache = 25% Local miss rate for 2-way set associateive L2 cache = 20% Miss penalty for L2 cache = 100 clock cycles What is the impact of second-level cache associativity on the miss penalty? - 5 - 14. (12) Assume that an L2 cache has a block size four times that of an L1. Show how a miss for an address that causes a replacement in L1 and L2 can lead to a violation of the inclusion prop- erty. - 6 - 15. (12) Given a disk with the following parameters: Av erage seek time = 5ms Transfer rate = 40MB/sec Rotation speed = 10,000 RPM Controller overhead = 0.1ms Assuming there is no queueing delay, what is the average time to read or write a 512-byte sector? What is the time assuming the average seek time is 3 times that of the measured seek time? - 7 -
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