Download Computer Architecture - Midterm Exam | ECS 201A and more Exams Computer Architecture and Organization in PDF only on Docsity! Very Short Answer: (1) (1) True or False: You can predict cache performance of Program A by analyzing Pro- gram B. (2) (2) What is the goal of the memory heirarchy? (3) (2) The memory heirarch works because of what two principles? (4) (4) List 4 of the 5 Miss Penalty Reduction Techniques. (5) (4) What are the 4 types of parallel processors, according to Flynn? (6) (1) What does COMA stand for? (7) (2) What does UMA and NUMA stand for? Short Answer: (1) (2) Briefly describe Interleaved Memory and how it works. (2) (2) What is a victim cache, and how does it work? (3) (2) What is the goal of the Virtual Memory system? (4) (2) What is Cache Coherence, and why is it necessary? (5) (4) Describe the difference between shared memory and message passing machines. Include the impact on design, cost, speed, and programming model. (8) (12) Assume a relatively large fully associative write-back cache that contains no valid data. Given the following sequence of 5 memory operations (the address of the operation is in the square brackets): WriteMem[100] WriteMem[100] ReadMem[200] WriteMem[200] WriteMem[100] What are the number of hits and misses when using write allocate versus no-write allo- cate? (9) (12) Suppose you want to achieve a speedup of 80 with 100 processors. What fraction of the original computation can be sequential? (10) (12) Assume that words A and B are in two different locations in the same cache block, which is in the shared state in the caches P1 and P2. In the following sequence of events, identify each miss as either a true sharing miss, a false sharing miss, or a hit. (Any miss that would occur if the block size were one word is referred to as a true sharing miss.) Time P1 P2 1 Write A 2 Read B 3 Write A 4 Write B 5 Read B For example, the event at time 1 is a true sharing miss, since A was read by P2 and needs to be invalidated from
