Computer-Based Scientific Instrument - Time Varying Signal | CEM 838, Study notes of Chemistry

Download Computer-Based Scientific Instrument - Time Varying Signal | CEM 838 and more Study notes Chemistry in PDF only on Docsity! November 9, 2004 - 1 - Version 2004.2 Time Varying Signals Chemistry 838 Thomas V. Atkinson, Ph.D. Senior Academic Specialist Department of Chemistry Michigan State University East Lansing, MI 48824 Table of Contents TABLE OF CONTENTS ............................................................................................................. 1 TABLE OF TABLES.................................................................................................................... 3 TABLE OF FIGURES.................................................................................................................. 4 1. OSCILLOSCOPE.................................................................................................................... 6 1.1. CRT...................................................................................................................................... 6 1.2. OSCILLOSCOPE SCHEMAT ..................................................................................................... 6 1.3. PROJECTION OF TWO TIME VARYING SIGNALS ....................................................................... 7 1.4. TIME SHARING THE BEAM..................................................................................................... 8 1.5. LISSAJOUS PATTERNS - VARYING PHASE ANGLE.................................................................. 9 1.6. LISSAJOUS PATTERNS - PHASE ANGLE MEASUREMENT ...................................................... 10 1.7. LISSAJOUS FIGURES - DIFFERENT FREQUENCIES ................................................................. 11 2. OSCILLOSCOPE (Y VERSUS TIME EXAMPLES)........................................................ 12 2.1. ASYNCHRONOUS SWEEP, WITH AND WITHOUT BLANKING................................................. 12 2.2. SYNCHRONIZED SWEEP....................................................................................................... 13 2.3. TRIGGERED SWEEP, SIMPLE SIGNAL ................................................................................... 14 2.4. TRIGGERED SWEEP, COMPLEX SIGNAL ............................................................................... 15 2.5. TRIGGERED SWEEP, COMPLEX SIGNAL ............................................................................... 16 3. RASTER DEVICES (TV, MONITOR) ON THE CRT ..................................................... 16 3.1. TIMING EXAMPLES.............................................................................................................. 16 3.1.1. Black and White .......................................................................................................... 17 3.1.2. Black and White (Multiple Frames Example) ............................................................. 18 3.1.3. Gray Scale ................................................................................................................... 19 3.1.4. Gray Scale (Multiple Frames Example)...................................................................... 20 3.1.5. Interlaced .................................................................................................................... 21 3.2. RASTER IMAGES.................................................................................................................. 22 3.2.1. Black and White .......................................................................................................... 22 Chemistry 838 Time Varying Signals Table of Contents November 9, 2004 - 2 - Version 2004.2 3.2.2. Gray Scale ................................................................................................................... 23 3.2.3. Interlaced .................................................................................................................... 24 4. CRT MODES SUMMARY ................................................................................................... 25 5. SWITCHES ............................................................................................................................. 26 5.1. IDEAL AND REAL ................................................................................................................. 26 5.2. MECHANICAL....................................................................................................................... 27 5.3. SOLID STATE ....................................................................................................................... 29 5.4. APPLICATIONS – MULTIVIBRATORS .................................................................................... 30 Monostable Applications........................................................................................................ 33 5.5. APPLICATIONS – ANALOG MULTIPLEXER ........................................................................... 34 6. MEASUREMENT OF TIME AND FREQUENCY ............................................................ 34 6.1. DEVICE ................................................................................................................................ 34 6.2. SIGNALS............................................................................................................................... 35 6.3. DERIVATION ........................................................................................................................ 35 6.4. REQUIREMENTS ................................................................................................................... 37 6.5. TIME BASE........................................................................................................................... 37 7. COMPUTER INTERFACE HARDWARE ........................................................................ 39 7.1. UNIPOLAR DAC.................................................................................................................. 40 7.1.1. Unipolar DAC Example (n = 4).................................................................................. 41 7.1.2. DAC Example (n = 4 with Error in Bit 2)................................................................... 42 7.1.3. DAC (Bipolar) ............................................................................................................. 44 7.2. SUCCESSIVE APPROXIMATION ADC ................................................................................... 46 7.2.1. Successive Approximation ADC Example (4 Bit Linear Search)................................ 46 7.2.2. Successive Approximation ADC Example (8 Bit Binary Search) ............................... 47 7.2.3. ADC Example 2 (8 Bit Binary Search)........................................................................ 48 7.3. DUAL SLOPE ADC .............................................................................................................. 50 7.4. FLASH ADC (2 BIT) ............................................................................................................ 52 8. MEASUREMENT AND CONTROL SYSTEMS – GENERAL ....................................... 53 9. ACQUISITION SYSTEMS (INPUT) - ANALOG ............................................................. 55 9.1. EFFECT OF RESOLUTION...................................................................................................... 55 9.2. ACQUISITION TIMING SCHEMES........................................................................................... 56 9.3. SIMPLE ADC....................................................................................................................... 57 9.4. OPERATOR TRIGGER ........................................................................................................... 59 9.5. SOFTWARE TRIGGER ........................................................................................................... 59 9.6. SIMPLE ADC WITH HARDWARE TRIGGER........................................................................... 61 9.7. PROGRAMMABLE CLOCK .................................................................................................... 62 9.8. PROGRAM ACCESS TO THE ADC AND A PROGRAMMABLE CLOCK ...................................... 63 9.9. DIRECT COUPLED CLOCK AND TRIGGER............................................................................. 65 9.10. SAMPLE/HOLD .................................................................................................................. 67 9.11. MULTIPLEXED INPUTS....................................................................................................... 68 9.12. LOCAL BUFFER, HARDWARE TRIGGER.............................................................................. 70 Chemistry 838 Time Varying Signals Table of Figures November 9, 2004 - 5 - Version 2004.2 FIGURE 51 - ACQUISITION SYSTEM WITH LOCAL BUFFER ............................................................................................71 FIGURE 52 - MULTIPLE ADC........................................................................................................................................73 FIGURE 53 - CIRCULAR BUFFER ...................................................................................................................................73 FIGURE 54 - PRE, MID, POST TRIGGERS........................................................................................................................73 FIGURE 55 - USING A LINEAR BUFFER AS A CIRCULAR BUFFER ...................................................................................75 FIGURE 56 - DIGITAL INPUT .........................................................................................................................................75 FIGURE 57 - DIGITAL INPUT II ......................................................................................................................................76 FIGURE 58 - SIMPLE DAC ............................................................................................................................................76 FIGURE 59 - DIGITAL OUTPUT......................................................................................................................................77 FIGURE 60 - EXTERNAL FREQUENCY/PERIOD/TIME/COUNT METER.............................................................................78 FIGURE 61 - INTERNAL FREQUENCY/PERIOD/TIME/COUNT METER..............................................................................79 FIGURE 62 - SIMPLE COMPUTERIZED ACQUISITION SYSTEM ........................................................................................82 FIGURE 63 - INTELLIGENT INSTRUMENT SYSTEM .........................................................................................................82 FIGURE 64 - DISTRIBUTED INSTRUMENT SYSTEM.........................................................................................................83 FIGURE 65 - A VERY DISTRIBUTED INSTRUMENT SYSTEM...........................................................................................83 FIGURE 66 - ONE TO ONE COMMUNICATION ................................................................................................................84 FIGURE 67 - PHYSICAL CONNECTIONS..........................................................................................................................84 FIGURE 68 – ONE-TO-MANY COMMUNICATION ...........................................................................................................85 FIGURE 69 - MULTICAST ..............................................................................................................................................85 FIGURE 70 - BROADCAST .............................................................................................................................................85 FIGURE 71 - COMMUNICATION TOPOLOGIES ................................................................................................................86 FIGURE 72 - HIERARCHY OF STARS ..............................................................................................................................87 FIGURE 73 - MIXED TOPOLOGIES .................................................................................................................................87 FIGURE 74 - HIGH DUTY CYCLE SIGNAL......................................................................................................................88 FIGURE 75 - LOW DUTY CYCLE SIGNAL.......................................................................................................................88 FIGURE 76 - LOWER DUTY CYCLE SIGNAL...................................................................................................................89 FIGURE 77 - LIMIT X-RANGE .......................................................................................................................................89 FIGURE 78 - LIMIT X-RANGE .......................................................................................................................................90 FIGURE 79 - LIMIT X AND Y RANGE.............................................................................................................................90 Chemistry 838 Time Varying Signals Oscilloscope November 9, 2004 - 6 - Version 2004.2 1. Oscilloscope The figures in this section are from Section 3-4 and following in "Making the Right Connection" 1.1. CRT 1.2. Oscilloscope Schemat Chemistry 838 Time Varying Signals Oscilloscope November 9, 2004 - 7 - Version 2004.2 1.3. Projection of two time varying signals Chemistry 838 Time Varying Signals Oscilloscope November 9, 2004 - 10 - Version 2004.2 1.6. Lissajous Patterns - Phase Angle Measurement sin Θ = c/b Chemistry 838 Time Varying Signals Oscilloscope November 9, 2004 - 11 - Version 2004.2 1.7. Lissajous Figures - Different Frequencies Horizontal to Vertical Frequencies a.) 1:1 b.) 2:1 c.) 1:5 d.) 10:1 e.) 5:3 Chemistry 838 Time Varying Signals Oscilloscope (y versus Time Examples) November 9, 2004 - 12 - Version 2004.2 2. Oscilloscope (y versus Time Examples) 2.1. Asynchronous Sweep, With and Without Blanking Chemistry 838 Time Varying Signals Oscilloscope (y versus Time Examples) November 9, 2004 - 15 - Version 2004.2 2.4. Triggered Sweep, Complex Signal Chemistry 838 Time Varying Signals Raster Devices (TV, Monitor) on the CRT November 9, 2004 - 16 - Version 2004.2 2.5. Triggered Sweep, Complex Signal 3. Raster Devices (TV, Monitor) on the CRT 3.1. Timing Examples Chemistry 838 Time Varying Signals Raster Devices (TV, Monitor) on the CRT November 9, 2004 - 17 - Version 2004.2 3.1.1. Black and White -15 -5 5 15 0 100 200 300 400 500 600 V er tic al -15 -5 5 15 0 100 200 300 400 500 600 H or iz on ta l -2 3 8 0 100 200 300 400 500 600 Time B ea m Chemistry 838 Time Varying Signals Raster Devices (TV, Monitor) on the CRT November 9, 2004 - 20 - Version 2004.2 3.1.4. Gray Scale (Multiple Frames Example) -15 -5 5 15 0 200 400 600 800 1000 1200 V er tic al -15 -5 5 15 0 200 400 600 800 1000 1200 H or iz on ta l -2 3 8 0 200 400 600 800 1000 1200 Time B ea m Chemistry 838 Time Varying Signals Raster Devices (TV, Monitor) on the CRT November 9, 2004 - 21 - Version 2004.2 3.1.5. Interlaced -15 -5 5 15 0 200 400 600 800 1000 1200 V er tic al -15 -5 5 15 0 200 400 600 800 1000 1200 H or iz on ta l -2 3 8 0 200 400 600 800 1000 1200 Time B ea m Chemistry 838 Time Varying Signals Raster Devices (TV, Monitor) on the CRT November 9, 2004 - 22 - Version 2004.2 3.2. Raster Images 3.2.1. Black and White 1 2 3 4 5 6 7 8 Pixel 1 2 3 4 5 6 7 8 H or iz on ta l L in e Raster (8 x 8) Display Black and White Horizontal flyback Vertical flyback Raster8x8.cdr 20-JUL-1997 T V Atkinson - Department fo Chemistry - Michigan State University Chemistry 838 Time Varying Signals CRT Modes Summary November 9, 2004 - 25 - Version 2004.2 4. CRT Modes Summary Type Horizontal Drive Vertical Drive Beam Drive X-Y plot remote signal source remote signal source on Time base Oscope (Simplest) local sweep generator (free running) remote signal source on Time base Oscope (Simple) local sweep generator (free running) remote signal source Blanked on flyback Time base Oscope Typical) local sweep generator (Triggered) remote signal source Blanked on flyback, when armed Raster (TV, Monitor) local sweep generator local sweep generator remote source (Beam Intensity contains the visual information for a given point (pixel) in the image being displayed.) The longer the persistence, the lower the refresh rate needed to keep an image visible. The longer the persistence, the slow the motion (i.e. the changes from one frame to the next, can be. Chemistry 838 Time Varying Signals Switches November 9, 2004 - 26 - Version 2004.2 5. Switches 5.1. Ideal and Real GenericSwitch_01.cdr 11-Oct-2004 Symbol VS iS Open Closed Figure 1 - Ideal Switch RealSwitch_01.cdr 11-Oct-2004 VS RSOpen RSClosed CS iS Figure 2 - Real Switch - 1st Order Model Table 1 shows nominal values for several of the figures of merit of switches. Any real switch also has a maximum value of VS. If a switch is subjected to voltages greater than the limit, the switch will arc and even catastrophically destruct. Another figure of merit is the maximum amount of current that can be put through the switch. Switches vary from a maximum current capacity of milliamps to many amps. Table 1 - Nominal Switch Characteristics Switch Type RSClosed RSOpen Time to Switch Ideal 0 ∞ 0 Mechanical <0.1Ω >100MΩ milliseconds Solid State <200Ω >1011Ω microseconds Figure 3 shows two symbols for switches that can be switched between the open and closed states by electronic rather than manual means. Such devices are used often in modern instrumentation. GenericSwitch_02.cdr 11-Oct-2004 Switchein ein eSC eout eout eSC Switch Control Figure 3 - Generic Switch with Electronic Control Chemistry 838 Time Varying Signals Switches November 9, 2004 - 27 - Version 2004.2 5.2. Mechanical Figure 4 - Mechanical Switch Chemistry 838 Time Varying Signals Switches November 9, 2004 - 30 - Version 2004.2 5.4. Applications – Multivibrators Monostable.cdr 30-SEP-2000 V R THRESH TRIG DISC Integrated Circuit OUT eref1 eC1 C eref0 eC0 to Close to Open Open Close Switch Control Switch Driver Monostable Configuration Figure 6 – Monostable Multivibrator Configuration Astablea.cdr 14-Oct-2004 V R1 R2 THRESH TRIG DISC Integrated Circuit OUT eref1 eC1 C eref0 eC0 to Close to Open Open Close Switch Control Switch Driver Figure 7 - Astable Multivibrator Configuration Chemistry 838 Time Varying Signals Switches November 9, 2004 - 31 - Version 2004.2 VC 0 TRIG eref1 eC1 eref0 eC0 Open Close Switch (OUT) 1 2 3 4 5 Monostabletime.cdr 30-SEP-2000 Assume C is discharged at t=0 Limitations: a.) Long = RC 1.) Leakage of C 2.) Noise on thresholds b.) Short = RC 1.) Speed of comparators 2.) Speed of switch 3.) Speed of discharge 4.) Stray capacitance t t 6 Figure 8 - Monostable Multivibrator Timing Chemistry 838 Time Varying Signals Switches November 9, 2004 - 32 - Version 2004.2 Open Close Switch (OUT) eC1 eC0 TRIG eref1 VC eref1 0 eref0 1 2 6 34 5 7 Astabletime.cdr 30-SEP-2000 Figure 9 - Astable Multivibrator Timing Chemistry 838 Time Varying Signals Measurement of Time and Frequency November 9, 2004 - 35 - Version 2004.2 FreqMeter_01.cdr 7-Oct-2003 egi egc ego estart estop Gate Control Gate Counter Figure 17 - Frequency/Period Measurement The Gate Control in Figure 17 is a circuit whose output, egc, will change state from Closed to Open upon detecting an edge (rising in the example) on estart. The output of the circuit will change from Open to Closed on the next edge of the appropriate type (rising in this example) on estop. The output of the gate is presented to the counter. Thus, the counter will count edges (rising in this example) of the signal, egi, coming from the gate when the gate is Open. 6.2. Signals An important case is that with the two inputs to the Gate Control tied together, i.e. driven by the same signal, egcin. Figure 18 illustrates the behavior of the device when presented the two periodic signals egi and egcin. FreqMeter_02.cdr 7-Oct-2003 egi pgi 0 1 0 1ego pgi tstart tstop 0 1e =e =gcin start estop ∆t egc Closed Open Figure 18 - Frequency/Period Measurement Timing 6.3. Derivation The following two relations are true in general. Chemistry 838 Time Varying Signals Measurement of Time and Frequency November 9, 2004 - 36 - Version 2004.2 period frequency 1= unittime riodsNumberofPefrequency = In the case of the Frequency/Period Measurement device as described here, the following will be true. In fact, the basis of all of the measurements accomplished with this device is the measurement of ∆t. gcstartstop pttt =−=∆ If the frequencies of the two input signals are integer multiples of each other, the following is true. Such a relationship of the two signals will be assumed for the derivation. The error in the measurement of ∆t due to this assumption is at most one period of egi. gcgiCounts ppn = These can be arranged as follows. gcgi Counts ff n 1 = gcCountsgi fnf = giCountsgc pnp = gc gi Counts f f n = gi gc Counts p p n = These results are the basis for the five measurement devices outlined in the table below. Chemistry 838 Time Varying Signals Measurement of Time and Frequency November 9, 2004 - 37 - Version 2004.2 Equation Device Conditions gcCountsgi fnf = Frequency Meter fgc is known giCountsgc pnp = Period Meter fgc is known Counts gc gi n f f = Frequency Ratio Meter Neither fgc nor fgi is known Counts gi gc n p p = Period Ratio Meter Neither fgc nor fgi is known giCountsstartstop pntt =− Elapsed Time Meter fgc is known Of course, egi and egcin are not always integral multiples of each other. Analysis of the possibilities will show that the error in the measurement of ∆t is one period of egi. This translates into the error in the 5 relationships in the table being at most 1 count when the two signals are not integral multiples. 6.4. Requirements The following constrains are required when applying the above to measurements. 1. The Gate control signal is always the slower, i.e. fgi > fgc. Otherwise, the number of counts accumulated will only be 0 or 1. 2. If one of the two signals is known, you can measure the other. If neither is known, you can only determine the ratio of the two unknown frequencies or the two unknown periods. 3. There is always an error in the measurement of ±1 count. Therefore, the number of counts should be as large as possible, i.e. fgi >> fgc to minimize the error of the measurement. 4. Both egi and egcin are periodic, except in the case of elapsed time measurement when only egi is periodic. 5. The accuracy and precision of the measurement is solely dependent on the accuracy and precision of the known frequency or period. 6.5. Time Base When measuring frequency or period, a stable, precise, accurate time base is needed as the standard or known signal. Figure 19 illustrates such a time base. The heart of the time base is an oscillator that is stabilized by a piezo electric crystal. Precisions and accuracies of parts per million and better can be achieved. In extreme cases, the temperature of the crystal will have to be stabilized. An appropriate output is chosen and connected to the Gate Input or the Gate Control. Chemistry 838 Time Varying Signals Computer Interface Hardware November 9, 2004 - 40 - Version 2004.2 7.1. Unipolar DAC eout ein b2b3 Switch Control b1 b0 DAC.cdr Rf R1 R2 R3 R0s0 s1 s2 s3 Figure 21 - Unipolar DAC Define the following binary variables. bi = 0 if switch Si is open bi = 1 if switch Si is closed Then the following is true ∑ − = −= 1 0 n i i i finout R bRee If the following is true, ii RR 2 = then i n i i f inout bR R ee 2 1 0 ∑ − = −= Notice that eout is an analog quantity, R R e fin− is an analog quantity, and i n i ib 2 1 0 ∑ − = is a binary number. The DAC outputs a voltage that ranges from 0 to (2n-1)* emax. The following defines emax. nf in R R ee 2max −= Chemistry 838 Time Varying Signals Computer Interface Hardware November 9, 2004 - 41 - Version 2004.2 or n f in eR Re −−= 2max Thus, as the input of the DAC goes from 0 to 2n-1, eout goes from 0 to max2 12 en n − in 2n steps. 7.1.1. Unipolar DAC Example (n = 4) Table 2 - DAC Circuit Parameters Parameter Value Rf/R 0.0625 ein -1 volt Table 3 - DAC Circuit Parameters (II) Parameter i 2i R0 0 1 R1 1 2 R2 2 4 R3 3 8 Table 4 - Unipolar DAC Example - Table of States Decimal b0 b1 b2 b3 Binary Multiplier Decimal Output 0 0 0 0 0 0 0 0.0000 1 1 0 0 0 1 1 0.0625 2 0 1 0 0 2 2 0.1250 3 1 1 0 0 3 3 0.1875 4 0 0 1 0 4 4 0.2500 5 1 0 1 0 5 5 0.3125 6 0 1 1 0 6 6 0.3750 7 1 1 1 0 7 7 0.4375 8 0 0 0 1 8 8 0.5000 9 1 0 0 1 9 9 0.5625 10 0 1 0 1 10 10 0.6250 11 1 1 0 1 11 11 0.6875 12 0 0 1 1 12 12 0.7500 13 1 0 1 1 13 13 0.8125 14 0 1 1 1 14 14 0.8750 15 1 1 1 1 15 15 0.9375 Chemistry 838 Time Varying Signals Computer Interface Hardware November 9, 2004 - 42 - Version 2004.2 4 Bit DAC Output 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 5 10 15 Binary Input Value O ut pu t V ol ta ge (- R F* Ei n* (S um (1 /R i)) Actual Output Ideal Output Figure 22 – Unipolar DAC Example - Transfer Function 7.1.2. DAC Example (n = 4 with Error in Bit 2) Table 5 - DAC with Error - Circuit Parameters Parameter Value Rf/R 0.0625 ein 1 volt Table 6 - DAC with Error - Circuit Parameters (II) Parameter i 2i R0 0 1 R1 1 2 R2 1.584963 3 R3 3 8 Chemistry 838 Time Varying Signals Computer Interface Hardware November 9, 2004 - 45 - Version 2004.2 Table 10 - Bipolar DAC Example - Table of States Decimal b0 b1 b2 b3 Binary Multiplier Decimal Output 0 0 0 0 0 0 0 -0.5000 1 1 0 0 0 1 1 -0.4375 2 0 1 0 0 2 2 -0.3750 3 1 1 0 0 3 3 -0.3125 4 0 0 1 0 4 4 -0.2500 5 1 0 1 0 5 5 -0.1875 6 0 1 1 0 6 6 -0.1250 7 1 1 1 0 7 7 -0.0625 8 0 0 0 1 8 8 0.0000 9 1 0 0 1 9 9 0.0625 10 0 1 0 1 10 10 0.1250 11 1 1 0 1 11 11 0.1875 12 0 0 1 1 12 12 0.2500 13 1 0 1 1 13 13 0.3125 14 0 1 1 1 14 14 0.3750 15 1 1 1 1 15 15 0.4375 4 Bit DAC Output -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 5 10 15 Binary Input Value O ut pu t V ol ta ge (- R F* Ei n* (S um (1 /R i)) Actual Output Ideal Output Figure 25 - Bipolar DAC Transfer Function Chemistry 838 Time Varying Signals Computer Interface Hardware November 9, 2004 - 46 - Version 2004.2 7.2. Successive Approximation ADC ADC0.cdr 25-Oct-2000 Number Generator/ Controller n-Bit Register Busy ConverteIn ea e < e ?a b eb eDAC Answer (n-Bit) DAC Switch Controls Figure 26 – Successive Approximation ADC 7.2.1. Successive Approximation ADC Example (4 Bit Linear Search) In this case a staircase is generated by incrementing a counter at a set rate until the generated voltage just exceeds the unknown voltage. Figure 27 is an example of how a 4 Bit ADC would operate. The bipolar 4-bit DAC from above is used to implement the 4-bit ADC. 1. Number Generator sets the counter to zero 2. Assert Convert to start process, raise Busy. 3. Number Generator adds 1 to the counter up at zero 4. If ea<eb, continue and go to Step 3, i. e. next count 5. If ea>eb, Done. Stop process, lower Busy. 6. Answer is the current contents of the n-bit Register. Table 11 - 4-Bit Successive Approximation ADC Signal Actual Voltage Steps required to get to answer Measured Voltage Unknown 1 0.26 13 0.3125 Unknown 2 -0.42 2 -0.3750 Chemistry 838 Time Varying Signals Computer Interface Hardware November 9, 2004 - 47 - Version 2004.2 4 Bit DAC Output -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 5 10 15 DAC Input Value (Step) D A C O ut pu t ( vo lts ) DAC Output Unknown 1 Unknown 2 Figure 27 - 4-Bit ADC Linear Search 7.2.2. Successive Approximation ADC Example (8 Bit Binary Search) • Start with MSB • Turn on bn.. Is eDAC > eunk? Yes – turn off bn No – Leave bn turned on • Turn on bn-1. Is eDAC > eunk? Yes – turn off bn-1 No – Leave bn-1 turned on • Continue through n = 0 Parameter Value Increment 0.00390625 Unknown 0.31 number of bits 8 Chemistry 838 Time Varying Signals Computer Interface Hardware November 9, 2004 - 50 - Version 2004.2 7.3. Dual Slope ADC eintegrator eunknown eknown Control ADCDualSlope.cdr ecomparator C R1 R0s0 s1 sc Figure 28 - Dual Slope ADC Table 12 - Dual Slope ADC - Switch Control Switch t0 tintegrate tdischarge (ta, tb, tc) sc closed open open s0 open closed open s1 open open closed ( ) integrate 0 unknown integrateintegrator tCR ete −= ( ) discharge 1 known integrateintegrator tCR ete −= ( ) discharge 1 known integrate 0 unknown integrateintegrator tCR e t CR ete −=−= 10 RR = discharge known integrate unknown t RC e t RC e −=− dischargeknownintegrateunknown te te = integrate discharge knownunknown t t e e = Chemistry 838 Time Varying Signals Computer Interface Hardware November 9, 2004 - 51 - Version 2004.2 eintegrator Time 0 0 ADCDualSlope2.cdr tintegratet0 tc tc tb ta tb ta Time ecomparator 0 1 Time ecomparator 0 1 Time ecomparator 0 1 Equal Slopes Figure 29 - Dual Slope ADC - Operation Chemistry 838 Time Varying Signals Computer Interface Hardware November 9, 2004 - 52 - Version 2004.2 7.4. Flash ADC (2 Bit) eunknown ADCFlash.cdr e0 b0 b1e1 e2 OVERFLOW ____________ UNDERFLOW R R R R Table 13 - Flash ADC - Table of States UNDERFLOW OVEROW e0 e1 e2 b0 b1 eref < eunknown 1 1 1 1 1 1 1 ¾ eref < eunknown < eref 1 0 1 1 1 1 1 ½ eref < eunknown < ¾ eref 1 0 1 1 0 1 0 ¼ eref < eunknown < ½ eref 1 0 1 0 0 0 1 0 < eunknown < ¼ eref 1 0 0 0 0 0 0 eunknown < 0 0 0 0 0 0 0 0 Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 55 - Version 2004.2 An experiment can be thought of a series of measurements of one or more dependent variables with time as the independent variable. An acquisition window, i. e. Figure 31, describes how the data is acquired for a given dependent variable. In essence, the measurement process is the discovery of the set of grid points of the acquisition window that are the closest to the signal or parameter being measured. Of course, what actually happens is that the point nearest the physical parameter for at tmin is determined and then that for the next time increment, etc. sequentially in time across the window. The goal is to optimize the window so that the signal being acquired fills the window giving the maximum resolution possible. The window is defined by the choices of the parameters tmin, tmax, ∆t, ymin, ymax, and ∆y. The choices are constrained by the needs of the experiment and the abilities of the acquisition system. Figure 31 shows a constant ∆t, which is the most common strategy. Figure 35 contains an example of an acquisition using equal acquisition intervals. Figure 37 and Figure 36 suggest other, nonlinear strategies that may be desirable. The ultimate goal is to gather the most information possible about the signal of interest. More data points are desired for the portion of a signal that is changing more rapidly. The implied quantized nature of the measurements in this discussion is slanted toward the use of Analog to Digital Converters to make the measurements. However, the use of analog oscilloscope, analog recorders, and manual recording to acquire a set of data is analogous. In those cases the ∆t and ∆y are the horizontal and vertical resolutions of the analog device. The best results occur for these devices when the signal being measured fills the oscilloscope display, the width of the recorder, etc. That is, the best results are when the signal fills the acquisition window. Another important consideration is the specification of tmin. Typically, the acquisition a signal is to begin at a particular time. Identifying that the time, i.e. the trigger event, has occurred must cause the acquisition to begin. 9. Acquisition Systems (Input) - Analog 9.1. Effect of Resolution 000 001 010 011 100 101 110 111 1000 0.000 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 0 5 10 15 20 25 Time A m pl itu de (D ec im al ) 0 1 2 3 4 5 6 7 8 0 5 10 15 20 25 A m pl itu de (B in ar y) Analog Digitized Figure 32 - Resolution - 3 Bits 0000 0010 0100 0110 1000 1010 1100 1110 10000 0.000 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 0 5 10 15 20 25 Time A m pl itu de (A na lo g) 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 A m pl itu de (B in ar y) Analog Digitized Figure 33 - Resolution - 4 Bits Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 56 - Version 2004.2 000000 001000 010000 011000 100000 101000 110000 111000 1000000 0.000 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 0 5 10 15 20 25 Time A m pl itu de (A na lo g) 0 8 16 24 32 40 48 56 64 0 5 10 15 20 25 A m pl itu de (B in ar y) Analog Digitized Figure 34 - Resolution - 6 Bits 9.2. Acquisition Timing Schemes -2 0 2 4 6 8 10 12 0 5 10 15 20 25 30 Time A m pl itu de Signal Timebase Figure 35 - Equal Acquisition Intervals -2 0 2 4 6 8 10 12 0 10 20 30 40 50 60 70 80 Time A m pl itu de Signal Timebase Figure 36 - Varied Acquisition Intervals -2 0 2 4 6 8 10 0 20 40 60 80 100 120 140 Time A m pl itu de Signal Timebase Figure 37 Exponential Acquisition Intervals Figure 38 illustrates a frequent need to acquire more than one signal at a time. A common approach is to use a multiplexed ADC which results the timing shown in Figure 39. Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 57 - Version 2004.2 -2 -1 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 Time A m pl itu de Signal 1 Timebase Signal 2 Figure 38 - Multiple Signals MultiplexADC.cdr 20-JUL-1997 yk zk yk+1 yk+2 zk+1 tk tk+1 tk+2 zk+2 ∆tacq ∆tData y(t) z(t) Figure 39 - Multiplexed ADC 9.3. Simple ADC This and the following sections will examine a number of approaches to implementing a computer interfaced acquisition system that will allow the acquisition of a set of points which represent the amplitude of one or more analog signals as a function of time. ADC1.cdr 7-Oct-1995 In ADC C SRConvert Busy d , ..., dn-1 0 eIn D at a World Computer In te rfa ce to I/ O B us Figure 40 - Simple ADC This simple system requires a program executing on the computer to cause the correct sequence of events to occur. The following sequence of operations will be performed by the program controlling the system. 1. Write a 1 into the Convert bit of the CSR, which will cause the ADC to begin a conversion. 2. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 3. Read the CSR and observe the value of the Busy bit. Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 60 - Version 2004.2 1. Write a 1 into the Convert bit of the CSR, which will cause the ADC to begin a conversion and raise the Busy flag. 2. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 3. Read the CSR and observe the value of the Busy bit. 4. If the Busy bit is 1, go to Step 3. If the Busy bit is 0, the conversion is finished, proceed to the next step. 5. Read the Data Register to get the converted point. 6. Compare the new value with Threshold? 7. If the new value is greater than the value in Threshold, go to Step 1. If the new value is less than the value in Threshold, the trigger mechanism is now armed, proceed to the next step. [Signal is now below the threshold. Get a new value and look for the next transition through the threshold.] 8. Write a 1 into the Convert bit of the CSR, which will cause the ADC to begin a conversion. 9. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 10. Read the CSR and observe the value of the Busy bit. 11. If the Busy bit is 1, go to Step 10. If the Busy bit is 0, the conversion is finished, proceed to the next step. 12. Read the Data Register to get the converted point. 13. Is the new value greater than or equal to the value stored in Threshold? 14. If no, go to Step 8. If yes, the trigger event has occurred, proceed with the acquisition of the dataset. This approach assumes, as with the triggering of an analog oscilloscope, that there is a slope and threshold that would define an unambiguous trigger event and that this trigger event would not occur until after the program has started. Figure 42 illustrates the timing of such an approach. The software is continually acquiring data points with an acquisition interval, ∆tacq. The software trigger is armed after the transition through the value stored in Threshold, which is detected with the data point acquired at time t1. The trigger event occurs at time t2. However, the fact that the trigger event has occurred is not detected until the data point is acquired at time t3. Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 61 - Version 2004.2 Acquision_02.cdr 20-Oct-2004t1 t2 t3 y ∆tacq Time Threshold Data Point Signal Figure 42 - Software Trigger Timing This approach could work for relatively slow signals. 9.6. Simple ADC with Hardware Trigger Another way to address the problem of when to begin the acquisition is to implement a hardware trigger mechanism as indicated in Figure 43. The trigger senses when the input signal, etrigger, crosses the threshold, ethreshold in the direction specified by the Slope, eSlope. ADC1.cdr 14-Oct-2004 In ADC C SRConvert Busy d , ..., dn-1 0 eIn D at a World Computer In te rfa ce to I/ O B us C SR In te rfa ce to I/ O B us In Trigger Trigger Arm etrigger ethreshold eslope Figure 43 - Simple ADC with Hardware Trigger Again, a program is required to cause the correct sequence of events to occur. The following sequence of operations will be performed by the program controlling the system. 1. Write a 1 into the Arm bit in the Trigger CSR. 2. Read the Trigger CSR and observe the value of the Trigger bit. 3. If the Trigger bit is 0, go to Step 2. If the Trigger bit is 1, a trigger event has occurred, proceed to the next step. Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 62 - Version 2004.2 4. Write a 1 into the Convert bit of the ADC CSR, which will cause the ADC to begin a conversion and raise the Busy flag. 5. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 6. Read the ADC CSR and observe the value of the Busy bit. 7. If the Busy bit is 1, go to Step 6. If the Busy bit is 0, the conversion is finished, proceed to the next step. 8. Read the ADC Data Register to get the converted point. 9. Store the point 10. Do the bookkeeping to see if more data points are to be taken and where the next data point is to be stored. 11. If more points are required, go to Step 1. If done, stop. [As written this program would take one data point per trigger. If the trigger is to signal that a set of points are to be acquired, the branch at this point would be to Step 4 instead.] This system addresses the problem of when to begin the process, i.e. an external trigger event will start the process. However, there will be some uncertainty in the timing of when the process begins. As with the Busy flag problem of the previous example, the number of instructions in the program that are executed between the time of the trigger event and when the program has sensed that the trigger event has occurred can vary from one run to the next. This approach does not address the time base challenge described above. 9.7. Programmable Clock 10 MHz Osc. M ul tip le xe r ( Sw itc h) Se le ct ed F re qu en cy 10 MHz 1 MHz 100 KHz 1 KHz 1 KHz 100 Hz 10 Hz 1 Hz /10 /10 /10 /10 /10 /10 /10 Freq Reg CSR I/O Bus Interface Not Shown: Control signals for strobing information into registers. En ab le C ou nt Gate 7 6 5 4 3 2 1 0 A0A1A2 CSR Counter (n-bits) En ab le O ve flo w La tc he d C lo ck O ut C le ar La tc he d C lo ck O ut Clock OutGate Preload Reg (n-bits) Counter Reg (n-bits) ProgClk1.cdr 1-Nov-2004 Flip Flop Set Q Clear Figure 44 - Programmable Clock Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 65 - Version 2004.2 [Wait for a clock tick, i.e. the end of a (beginning of next) time interval.] 8. Read the Programmable Clock CSR and observe the value of the Latched Clock Out bit. 9. If the Latched Clock Out bit is 0, go to Step 8. If the Latched Clock Out bit is 1, a time interval has occurred, proceed to the next step. 10. Write a 1 into the Clear Latched Clock Out bit in the Programmable Clock CSR to clear the latch and, thus, prepare for the end of the current interval. [Acquire a data point.] 11. Write a 1 into the Convert bit of the ADC CSR, which will cause the ADC to begin a conversion. 12. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 13. Read the CSR and observe the value of the Busy bit. 14. If the Busy bit is 1, go to Step 13. If the Busy bit is 0, the conversion is finished, proceed to the next step. 15. Read the ADC Data Register to get the converted point. 16. Store the point 17. Do the bookkeeping to see if more data points are to be taken, and where the next data point is to be stored. 18. If more points are required, go to Step 8. If done, Stop. [As this program is written, the trigger event signals that a set of n data points are to be acquired.] This system addresses the two problems above, i.e. the time base and triggering. By choosing the appropriate basic time base and preload value for the Programmable Clock, a wide range of time intervals can be selected. However, there is still a problem with the timing. The clock overflows that mark the end of the time intervals are sensed by the the software “spinning on a bit.” Since the Programmable Clock and the Computer are separate asynchronous machines, the reading of the overflow flag may not occur immediately. If the overflow flag goes up right after the program has read the overflow flag, then the event will not be noticed until a few instruction times later when the program loop comes back around and senses the flag again. This uncertainty decreases the precision of the time base. 9.9. Direct Coupled Clock and Trigger In order to increase the precision of the timing, the Programmable Clock and the trigger can be directly connected to the ADC as indicated in Figure 46. Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 66 - Version 2004.2 ADC3.cdr 16-Oct-2004 Not Shown: Control signals required to strobe signals onto and off of the I/O Bus. In ADC Convert Busy d , ..., dn-1 0 eIn D at a R eg C SR In te rfa ce to I/ O B us World Computer C SR In te rfa ce to I/ O B us In Trigger Trigger Arm etrigger ethreshold eslope Prog. Clock Base Freq Select Preload Reg Counter Enable Count Latched Clock Out Clear Latched Clock Out Clock Out D at a R eg D at a R eg D at a R eg Enable Overflow C SR In te rfa ce to I/ O B us Figure 46 - Acquisition System with Direct Coupled Clock and Trigger The following steps would be required of the program to acquire n points separated by equal increments of time. [Set up the Programmable Clock and the Trigger.] 1. Write the choice of the basic time base into the Programmable Clock Base Freq Select register. 2. Write a 1 into the Enable Overflow bit in the Programmable Clock CSR to allow the overflow to be output when it occurs. 3. Write the number of intervals of the basic time base between data points into the Programmable Clock Preload Reg. 4. Write a 1 into the Arm bit in the Trigger CSR. [The trigger event will start both the ADC and the Programmable Clock.] [Acquire a data point.] 5. Read the ADC CSR and observe the value of the Busy bit. 6. If the Busy bit is 1, go to Step 5. If the Busy bit is 0, the conversion is finished, proceed to the next step. Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 67 - Version 2004.2 7. Read the ADC Data Register to get the converted point. 8. Store the point 9. Do the bookkeeping to see if more data points are to be taken, and where the next point is to be stored. 10. If more points are required, go to Step 5. If done, Stop. This system will have more precise triggering and timing, since the vagaries of the program execution are now removed from the timing. 9.10. Sample/Hold Most ADCs require that the voltage being measured be constant over the interval of time during which the conversion takes place. The Sample and Hold (an analog latch) depicted in Error! Reference source not found. and Error! Reference source not found. captures the value of the signal being measured at the beginning of the conversion interval and holds that value until the conversion is done. SampleHold.cdr 5-Nov-2002 Figure 47 - Sample and Hold Tr ig ge r e ve nt o cc ur s S/ H S et tle s A to D C on ve rs io n Be gi ns A to D C on ve rs io n en ds Data Point is stored A rm th e tri gg er Next point can begin Signal Output of Sample and Hold ADC6.cdr 17-Apr-2000 tADCtS to H tH to S Figure 48 - Sample and Hold – Time Course Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 70 - Version 2004.2 8. Read the ADC Data Register to get the converted point. 9. Store the point, x(ti). [Get the next z(ti).] 10. Write the binary number 1 into the a2, a1, and a0 bits of the Multiplexer CSR, which will cause e1 to be presented to the input of the Sample/Hold. 11. Write a 0 into the Sample bit of the CSR, which will cause the Sample/Hold to follow the input signal. 12. At the time the conversion is to begin, write a 1 into the Sample bit of the Sample/Hold CSR, which will cause the Sample/Hold to hold the current value of the input signal. 13. Write a 1 into the Convert bit of the ADC CSR, which will cause the ADC to begin a conversion. 14. Write a 0 into the Convert bit of the CSR. This rearms the Convert bit in preparation for the next conversion. The ADC is undisturbed by this step. 15. Read the ADC CSR and observe the value of the Busy bit. 16. If the Busy bit is 1, go to Step 15. If the Busy bit is 0, the conversion is finished, proceed to the next step. 17. Read the ADC Data Register to get the converted point. 18. Store the point, z(ti). 19. Do the bookkeeping to see if more data points are to be taken, and where the next data points are to be stored. 20. If no more points are required, stop. Otherwise, proceed with the next step. [Kill some time before the next pair of points is to be acquired] 21. Get the contents of the location Time Delay. 22. Subtract 1. 23. If the result is 0, go to Step 1. If the result is > 0, go to Step 21. Again as described, this system has the same problem of sensing a trigger event. In addition having a more deterministic, stable, accurate time base would probably be desirable. A real system would address these issues, most likely by combining the elements of Figure 50 with others discussed in this section. 9.12. Local Buffer, Hardware Trigger Often even more functionality is moved from the program into the acquisition system in order to increase the performance of the acquisition process. Typically, the logic of all of the operation can be simplified and implemented in hardware leading to increased performance. Figure 51 illustrates one such system. Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 71 - Version 2004.2 ADC7.cdr 15-Oct-2004 In ADC Convert Busy Trigger d , ..., dn-1 0 eIn In Trigger etrigger ethreshold eslope Local Buffer for Data World Computer In te rfa ce to I/ O B us Sample/ Hold Out Sample In Prog. Clock Base Freq Select Preload Reg Counter Enable Count Latched Clock Out Clear Latched Clock Out Clock Out D at a R eg D at a R eg D at a R eg Enable Overflow C SR In te rfa ce to I/ O B us Figure 51 - Acquisition System with Local Buffer The program that will run on the computer to operate this system is below. [Set up the Programmable Clock and the Controller.] 1. Write the choice of the basic time base into the Programmable Clock Base Freq Select register. 2. Write the value for up counting into the bit named UP in the Programmable Clock CSR 3. Write a 1 into the Enable Overflow bit in the Programmable Clock CSR to allow the overflow to be output when it occurs. 4. Write the number of intervals of the basic time base between data points into the Programmable Clock Preload Reg. 5. Write the number of data points to be acquired into the Controller. 6. Write the address of the desired multiplexer input into the Controller. 7. Write a 1 into the Start bit of the Controller CSR. This will start the process. Controller will raise the Controller Busy flag. [Wait for the data set to be acquired.] 8. Read the Controller CSR and observe the value of the Busy bit. 9. If the Busy bit is 1, go to Step 8. If the Busy bit is 0, the acquisition is finished, proceed to the next step. 10. Transfer the dataset from the local buffer to computer memory. Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 72 - Version 2004.2 11. Stop. The Controller must perform the following steps upon receiving the start command. 1. Raise the Controller Busy flag. 2. Write the binary number of the input signal to be acquired into the a2, a1, and a0 bits of the Multiplexer, which will cause the desired signal to be presented to the input of the Sample/Hold. 3. Write a 0 into the Sample bit of the CSR, which will cause the Sample/Hold to follow the input signal. 4. At the time the conversion is to begin, write a 1 into the Sample bit of the Sample/Hold CSR, which will cause the Sample/Hold to hold the current value of the input signal. 5. Write a 1 into the Convert bit of the ADC, which will cause the ADC to begin a conversion. 6. Read the value of the ADC Busy bit. 7. If the Busy bit is 1, go to Step 6. If the Busy bit is 0, the conversion is finished, proceed to the next step. 8. Write a 0 into the Sample bit of the CSR, which will cause the Sample/Hold to follow the input signal while other tasks are going on. 9. Read the ADC Data Register to get the converted point. 10. Store the point in the local buffer. 11. Do the bookkeeping to see if more data points are to be taken, and where the next is to be stored. 12. If more points are required, go to Step 3. If done, lower Controller Busy flag. 9.13. Multiple ADCs The offset, ∆tacq in Figure 38, between the time a point from one signal is acquired and the time a point from a second signal is acquired can be eliminated with the use of multiple ADCs as depicted in Figure 52. Notice that Convert inputs of all of the ADCs are driven by the same clock signal. The computer program sets up the programmable clock before the acquisition begins. Once the acquisition begins, the program monitors the Busy flags. When the conversions are finished, the program reads the output data of the ADC and stores the data for later analysis. Chemistry 838 Time Varying Signals Acquisition Systems (Input) - Analog November 9, 2004 - 75 - Version 2004.2 CircularBuffer0.cdr 26-Oct-2004 Next Element Next Element Next Element Next Element a1 a2 a3 a4 a5 a6 a7 a8 a17 a9 a18 a10 a19 a11 a20 a12 a21 a13 a22 a14 a23 a15 a24 a16 a113 a114 a115 a116 a117 a118 a119 a120 a121 a122 a123 a100 a101 a102 a103 a104 a105 a106 a107 a108 a109 a110 a111 a112 a1 a2 a3 a4 a5 a17 a18 a19 a20 a21 a22 a23 a24 a25 a26 a27 a28 a29 a30 a31 a8 a9 a10 a11 a12 a13 a14 a15 a16 Buff Buff + 1 Buff + 2 Buff + 3 Buff + 4 Buff + 5 Buff + 6 Buff + 7 Buff + 8 Buff + 9 Buff + 10 Buff + 11 Buff + 12 Buff + 13 Buff + 14 Buff + 15 Buff + 16 Buff + 17 Buff + 18 Buff + 19 Buff + 20 Buff + 21 Buff + 22 Buff + 23 Buffer Contains Elements none a - a1 5 a - a1 24 a - a8 31 a - a100 123 t24 After Acquisition time t31t5 t123 Next Element Before the start Figure 55 - Using a Linear Buffer as a Circular Buffer 9.15. Acquisition Systems - Digital Figure 56 illustrates an 8 bit Digital Input system. If the experimental apparatus, i. e. the various domain converters and transducers, produce a series of digital values, the system of this section could be used to acquire the data. DigitalIn_00.cdr 27-Oct-2004 Control Latch 0 1 3 4 5 6 7 D at a World Computer In te rfa ce to I/ O B us C SR Figure 56 - Digital Input As before a program is required to cause the correct sequence of events to occur. The following sequence of operations will be performed by the program controlling the system. Chemistry 838 Time Varying Signals Control of the Experiment, Output November 9, 2004 - 76 - Version 2004.2 1. Write a 0 into the Control bit of the CSR, which will cause the Latch to follow the input signals. 2. Write a 1 into the Control bit of the CSR, which will cause the Latch to hold the current values of the input signals. 3. Read the Data Register to get the new set of bits. 4. Store the store the set of bits. 5. Do the bookkeeping to see if more data points are to be taken, and where the next data appoint is to be stored. 6. If more points are required, go to Step 1. If done, stop. As with the simple ADC, this approach ignores the issues of when to start acquiring the data and how to control the intervals of time between successive acquisitions of sets of binary bits. Figure 57 illustrates a slight variant where the external system signals that a new point is ready by strobing the Data Ready signal. In such a case, the program would have to monitor the Data Ready bit and get the new point when it has been latched into the interface. DigitalIn_01.cdr 27-Oct-2004 Control Latch 0 1 3 4 5 6 7 D at a World Computer In te rfa ce to I/ O B us C SR Figure 57 - Digital Input II These issues with triggering and acquisition interval could be addressed by adding triggers, programmable clocks, local buffers, and such to the system in ways analogous to the analog acquisitions cases discussed above. 10. Control of the Experiment, Output 10.1. Analog DAC_10.cdr 27-Oct-2004 Out DAC d , ..., dn-1 0 eout Da ta World Computer In te rfa ce to I/ O B us Figure 58 - Simple DAC Chemistry 838 Time Varying Signals Control of the Experiment, Output November 9, 2004 - 77 - Version 2004.2 Figure 58 illustrates an analog output system. In this case, the program writes the next value to be converted and output into the Data Register at the proper moment. The value becomes available as soon as the DAC does the conversion. More careful control of when the points are output can be achieved by including a programmable clock with the system. Another variant consists of adding a local buffer which can be preloaded with a set of values to be output. This approach removes the computer from the output once the local buffer has been loaded. These techniques would be very similar to those discussed in the analog acquisition section. Such analog output systems can be used to output very complex functions, i.e. be a function generator. 10.2. Digital DigitalOut_00.cdr 27-Oct-2004 Control Latch 0 1 3 4 5 6 7 D at a World Computer In te rfa ce to I/ O B us C SR Figure 59 - Digital Output Figure 59 illustrates a digital output system. The Data Ready signal strobes the data into the latch to hold it for the external system. The Data Ready signal also serves as a flag to signal the external system that a new value has been output. Chemistry 838 Time Varying Signals Figures of Merit for Acquisition System Components November 9, 2004 - 80 - Version 2004.2 12. Figures of Merit for Acquisition System Components 12.1. DAC • Resolution (number of bits) • Output range (vmin to vmax) • Output current limit • What happens if the output is shorted? • Time to convert a number • Linearity • Cost • Power Consumption • Heat dissipation 12.2. ADC • Resolution (number of bits) • Input range (vmin to vmax) for conversion • Input range (vmin to vmax) for safety of the ADC device • Time to convert a number • Linearity • Cost • What happens if the inputs are overloaded? • Power Consumption • Heat dissipation 12.3. Multiplexer • Number of inputs • Input range (vmin to vmax) assume the same for each input • Time to switch from one input to another • Cost • What happens if the inputs are overloaded? • Power Consumption • Heat dissipation Chemistry 838 Time Varying Signals Figures of Merit for Acquisition System Components November 9, 2004 - 81 - Version 2004.2 12.4. Sample and Hold • Input range (vmin to vmax) • Time to go from sample to hold • Time to go from hold to sample • Droop rate • Cost • What happens if the inputs are overloaded? • Power Consumption • Heat dissipation 12.5. Counter • Resolution (number of bits) • Maximum count rate • Cost • Power Consumption • Heat dissipation Chemistry 838 Time Varying Signals Instrument Systems November 9, 2004 - 82 - Version 2004.2 13. Instrument Systems Instrument_01.cdr 2-Nov-2004 Control Bus Address Bus Data Bus CPU Memory Control Panel Registers Arithmetic Logical Unit Command Decoder I/O Controller #1 Registers Display/ Controls I/O Controller #2 Registers Analog In Analog Out Digital Out Digital In Freq Meter Acquisition System Controller Figure 62 - Simple Computerized Acquisition System Instrument_02.cdr 2-Nov-2004 Control Bus Address Bus Data Bus CPU Communication Channel Memory Control Panel Registers Arithmetic Logical Unit Command Decoder I/O Controller #1 Registers Display/ Controls I/O Controller #2 Communication I/O Controller Registers Analog In Analog Out Digital Out Digital In Freq Meter Acquisition System Controller Figure 63 - Intelligent Instrument System Chemistry 838 Time Varying Signals Communication (A Brief Introduction) November 9, 2004 - 85 - Version 2004.2 14.2. Many Participants Usually there are many more than two participants connected to a communication facility. One mode of operation in such cases is for there to be one talker and any number of listeners as depicted in Figure 68. One node can talk to a subset of the population as shown in Figure 69. Or, the information can be sent to all participants as in Figure 70. Talker Listner Listner Listner Network_02.cdr 4-Nov-2004 Figure 68 – One-to-Many Communication Network_04.cdr 4-Nov-2004 A B C E F D Figure 69 - Multicast Network_04.cdr 4-Nov-2004 A B C E F D Figure 70 - Broadcast Notice that the discussion so far seems to assume that there is a communication channel between the talker and each of the listeners. As the number of participants grows, this becomes more difficult to achieve. Figure 71 illustrates a few variations of communication systems connecting 6 participants. Except for the case of the communication bus, shared link, or party line depicted in Figure 71g, all communication systems are a combination of one-to-one communication channels connecting two participants. Figure 71a illustrates the case where there is a dedicated link between each pair of participants. Except in the case of the bus, the communication between two nodes may involve more than the two communicating participants. In such cases, the information must pass through intermediate nodes to get to the destination. As an example, assume the topology of Figure 71b. If node F wishes to communicate with node E, all information must first pass to node A, which then must forward the information to the destination. More hops are involved in other cases. In these cases of less than full connectivity, the interior nodes may be dedicated to forwarding information and not be full fledged nodes as those on the fringes of the topology. These interior forwarding nodes may be hubs, switches, routers, or gateways. Chemistry 838 Time Varying Signals Communication (A Brief Introduction) November 9, 2004 - 86 - Version 2004.2 The topology of Figure 71g does not need the forwarding nodes, but the communication channel is shared and one conversation has to wait until the current one is finished. Network_05.cdr 4-Nov-2004 d. Arbitrary b. Star g. Bus (party line) f. Daisy Chain a. Fully Connected c. Tree e. Ring A B CE F D A B CE F D A B C E FD A B C E F D A B C E F D A B C E FD E F D C B A Figure 71 - Communication Topologies From a communication point of view, the topology of Figure 71a is the most desirable in that there is a dedicated communication link to all other parties. Thus, communication between any two nodes can take place with no interference from any other conversations. In all other cases, there are conflicts that may impede any given conversation between two nodes. However, there are two facts that keep any real network from striving toward the goal of full connectivity. First, a human being and most machines are limited in the number of conversations in which they can participate simultaneously. Second, the number of links required to fully connect a group of nodes grows very rapidly with the number of nodes. Equation 1 shows the relationship between the number of links, k, and the number of nodes, n, to be connected in a fully connected topology. !2)!2( ! − = n nk Equation 1 Table 15 tabulates some values from this equation. Chemistry 838 Time Varying Signals Communication (A Brief Introduction) November 9, 2004 - 87 - Version 2004.2 Table 15 - Number of Links in a Fully Connected Net Number of Nodes Number of Links Number of Nodes Number of Links 2 1 10 45 3 3 20 190 4 6 28 378 5 10 50 1225 6 15 100 4950 7 21 200 19900 8 28 500 124750 9 36 10000 49995000 10 45 100000 5E+09 As an example, consider the city of Lansing, MI which has about 400000 inhabitants with, say as a guess, 100000 households. A completely connected telephone network for this community would require 5x109 phone lines between each home and every other house. But even worse, each home would have to have 5x109 telephone instruments. Absurd! Figure 72 illustrates a more complicated topology than those of Figure 71 and involves 28 full nodes, 6 forwarding only nodes (i.e. hubs, Hi) and 33 links. This set of nodes would require 378 links to completely connect the 28 full nodes, already an unwieldy number. Real systems can be much more complicated even if they are not fully connected. For example, consider the global phone network or the global Internet each with millions of nodes. At the other extreme are small local area networks involving only a small number of nodes. Any network will be a compromise between the number of links and the desire for connectivity, and will be extensions of the concepts included in Figure 71, Figure 72, and Figure 73. StarHierarchy.cdr 17-Nov-2002 C1 C5 C4 C6 C3 H3 C2 D1 D5 D4 D6 D3 H4 D2 B1 B2 B3B4 B5 H2 A1 A5 A4 A6 A3 H1 A2 E1 E2 E3E4 E5 H5 H6 Figure 72 - Hierarchy of Stars MixedTopology.cdr 19-Nov-2002 D1 D5 D4 D6 D3 H4 D2 F1 F5 F4 F6 F3 F2 G1 G4G3G2 B1 B2 B3B4 B5 H2 A1 A5 A4 A6 A3 H1 A2 E1 E2 E3E4 E5 H5 H6 C1 C5 C4 C6 C3 H3 C2 Figure 73 - Mixed Topologies Chemistry 838 Time Varying Signals Time Varying Signal Details November 9, 2004 - 90 - Version 2004.2 Signal Detail -5 0 5 10 15 20 25 30 15 25 35 Time A m pl itu de Figure 78 - Limit X-Range Signal Detail 15 17 19 21 23 25 27 15 25 35 Time A m pl itu de Figure 79 - Limit X and Y Range 15.3. Signal Details - Another part of the Signal Signal Detail 5 7 9 11 13 15 17 19 70 80 90 100 Time A m pl itu de Signal Detail 15 17 19 21 23 25 27 15 25 35 Time A m pl itu de Signal Detail 5 7 9 11 13 15 17 19 70 80 90 100 Time A m pl itu de Chemistry 838 Time Varying Signals Time Varying Signal Details November 9, 2004 - 91 - Version 2004.2 15.4. Acquisition Strategies – Scenario 1 -5 0 5 10 15 20 25 30 0 500 1000 1500 2000 2500 3000 3500 Time Am pl itu de Acquisition Window Acquisition_10.cdr 2-Nov-2004 Lower Duty Cycle Signal -5 0 5 10 15 20 25 30 0 500 1000 1500 2000 2500 3000 3500 Time A m p l i t u d e Acquisition Window 15.5. Acquisition Strategies – Scenario 2 Lower Duty Cycle Signal -5 0 5 10 15 20 25 30 0 500 1000 1500 2000 2500 3000 3500 Time A m p l i t u d e Acquisition Window Chemistry 838 Time Varying Signals Time Varying Signal Details November 9, 2004 - 92 - Version 2004.2 Lower Duty Cycle Signal -5 0 5 10 15 20 25 30 0 500 1000 1500 2000 2500 3000 3500 Time A m p l i t u d e Acquisition Window Lower Duty Cycle Signal -5 0 5 10 15 20 25 30 0 500 1000 1500 2000 2500 3000 3500 Time A m p l i t u d e Acquisition Window 15.6. Acquisition Strategies – Scenario 3 Lower Duty Cycle Signal -5 0 5 10 15 20 25 30 0 500 1000 1500 2000 2500 3000 3500 Time A m p l i t u d e Acquisition Window