Computer Buses - Principles of Computer Architecture - Lecture Slides, Slides of Advanced Computer Architecture

Download Computer Buses - Principles of Computer Architecture - Lecture Slides and more Slides Advanced Computer Architecture in PDF only on Docsity! Computer Buses – A bus is a common electrical pathway between multiple devices. • Can be internal to the CPU to transport data to and from the ALU. • Can be external to the CPU, to connect it to memory or to I/O devices. – Early PCs had a single external bus or system bus. – Modern PCs have a special-purpose bus between the CPU and memory and (at least) one other bus for the I/O devices. Docsity.com Computer Buses CPU chip Buses Registers Bus Memery bus S| controllers [= ]_—sMermary U0 bus On-chip bus Disk Modem Printer Figure 3-34. A computer system with multiple buses. Docsity.com Computer Buses – Some devices that attach to a bus are active and can initiate bus transfers. They are called masters. – Some devices are passive and wait for requests. They are called slaves. – Some devices may act as slaves at some times and masters at others. – Memory can never be a master device. Docsity.com Computer Buses • The binary signals that computer devices output are frequently not strong enough to power a chip. – The bus may be relatively long or have several devices attached to it. – Most bus masters are connected to the bus by a chip called a bus driver which is essentially a digital amplifier. – Most slaves are connected to the bus by a bus receiver. Docsity.com Computer Buses – For devices which can be both master and slave, a device called a bus transceiver is used. – These bus interface devices are often tri-state devices to allow them to disconnect when they are not needed. – A bus has address, data, and control lines, but there is not necessarily a one-to-one mapping between CPU pins and bus lines. A decoder chip between CPU and bus would be needed in this case. Docsity.com Bus Width – The number of data lines needed also tends to increase over time. – There are two ways to increase the data bandwidth of a bus: • decrease the bus cycle time • increase the data bus width – Speeding up the bus results in problems of bus skew since data on individual lines travel at slightly different speeds. This also makes the bus non- compatible with pre-existing devices. Docsity.com Bus Width – Therefore, an increased data width is the usual answer (e.g. in the PC which went from 8 data lines to 16 and then to 32 on essentially the same bus). – Another solution is to use a multiplexed bus. – The same lines are used for both data and addressing by breaking up the bus operation into multiple steps. This slows down bus performance. Docsity.com Bus Clocking – Buses can be divided up into two categories depending on their clocking. – A synchronous bus has a line driven by a crystal oscillator. • The signal on this line consists of a square wave with a frequency of 5 - 100 MHz. • All bus activities take an integral number of these cycles, called bus cycles. – The asynchronous bus does not have a master clock. Bus cycles can be of any length required and need not be the same. Docsity.com Bus Clocking – Although synchronous buses are easy to work with due to their discrete time intervals, they also have some problems. • Everything works in multiples of the bus clock. • If a CPU and memory can complete a transfer in 3.1 cycles they have to stretch it to 4.0 because fractional cycles are forbidden. • Once a bus cycle has been chosen, and memory and I/O cards have been built for it, it is difficult to take advantage of future improvements in technology. The bus has to be geared to the slowest devices (legacy devices) on the bus. Docsity.com Bus Clocking – Mixed technology can be handled by going to an asynchronous bus. – The master device asserts MREQ’, RD’, etc. and then asserts MSYN’ (Master SYNchronization). • Seeing this, the slave device starts to work. • When it is finished it asserts SSYN’ (Slave SYNchronization). • Seeing this, the master reads the data. • When it is done, it negates MREQ’, RD’, the address lines, MSYN’ and SSYN’. Docsity.com Bus Clocking • This ends the read. – A set of signals that interlocks in this way is called a full handshake. – Full handshakes are timing independent. Each event is caused by a prior event, not by a clock cycle. – Despite the advantages of asynchronous buses, most buses are synchronous since they are easier to build, and since there is such a large investment in synchronous bus technology. Docsity.com Bus Arbitration Pape File Edit Options View Orientation Media Help File: figs-.ps 485, 381pt_ Page: 40" 40 of 8 4 Bus request Bus grant Arbiter | fei? MS Bus grant - - may or may not 1 2 3 4 5 be propagated along the chain VO devices ta) Bus request level 1 Bus request level 2 Arbiter |_ Bus level 2 Bus: level 1 tb) Figure 3-39. (a) A centralized one-level bus arbiter using daisy chaining. (b) The same arbiter, but with two levels. aA Docsity.com Bus Arbitration – In the first scheme shown, the closest device always wins. – In the second scheme, there are multiple levels of priority. A device assert the line for its priority, and the arbiter grants the request by asserting the line with the highest priority. – Since the CPU must compete for the device on most every cycle (i.e. it must read a word of memory) the memory is often put on a separate bus from the I/O devices so it doesn’t have to compete. Docsity.com Bus Arbitration – Decentralized bus arbitration is also possible. • A computer could have 16 prioritized bus request lines. When a device wants to use the bus, it assert its request line. • All devices monitor all request lines, so at the end of each bus cycle, each device knows whether it was the highest priority requester. • This method avoids the necessity of an arbiter, but requires more bus lines. • Another decentralized scheme equivalent to the daisy chain arbitration minus the arbiter is shown on the following slide. Docsity.com 2 ADDRESS Bus Operations PUPLIELELE LP Lee YX Memory addrass to be read x = xX YOKE | | ) | | | Figure 3-41. A block transfer. Docsity.com Bus Operations – Another important kind of bus cycle is for handling interrupts. When the CPU commands an I/O device to do something, it usually expects an interrupt when the work is done. The interrupt signaling requires the bus. – Since multiple devices may want to cause an interrupt simultaneously, the same kind or arbitration problems we had with ordinary bus cycles are present. • The usual solution is to assign priorities and use a centralized arbiter. Docsity.com Bus Operations – Standard interrupt controller chips exist and are widely used. – The IBM PC and all its successors use the Intel 8259A chip. – Up to eight I/O controllers can be directly connected to the eight IR inputs to the 8259A. When one of these devices wants to cause an interrupt, it asserts its input line. • When one or more interrupts are asserted, the 8259A asserts INT which drives the interrupt pin on the CPU. Docsity.com