ECE 15B Spring 2009 HW Solutions: Base Conversion, Boolean Algebra, Timing Diagram, Assignments of Mechanical Engineering

Download ECE 15B Spring 2009 HW Solutions: Base Conversion, Boolean Algebra, Timing Diagram and more Assignments Mechanical Engineering in PDF only on Docsity! ECE 15B Spring 2009 1 of 6 University of California, Santa Barbara ECE 15B COMPUTER ORGANIZATION Homework #1 SOLUTIONS 1. Number Base Conversion (20 Points) ( a ) (5 points) Convert 1100011110012 to its decimal representation The number 011111001101 in base 2 represents: ( 1* 2^11 ) + ( 1* 2^10 ) + ( 0* 2^9 ) + ( 0* 2^8 ) + ( 0* 2^7 ) + ( 1* 2^6 ) + ( 1* 2^5 ) + ( 1* 2^4 ) + ( 1* 2^3 ) + ( 0* 2^2 ) + ( 0* 2^1 ) + ( 1* 2^0 ) which is 1*2048 + 1*1024 + 0*512 + 0*256 + 0*128 + 1*64 + 1*32 + 1*16 + 1*8 + 0*4 + 0*2 + 1*1 So, the answer is: 3,19310 ( b ) (5 points) Convert 1100011110012 to its octal representation 110 | 001 | 111 | 001 6 1 7 1 So the answer is: 61718 ( c ) (5 points) Convert 1100011110012 to its hexadecimal representation 1100 | 0111 | 1001 C 7 9 So the answer is: C7916 ECE 15B Spring 2009 2 of 6 ( d ) (5 points) Convert the decimal number 0.14110 to an 8-bit binary number 0.141 x 2 0.282 0 x 2 0.564 0 x 2 1.128 1 x 2 0.256 0 x 2 0.512 0 x 2 1.024 1 x 2 0.048 0 x 2 0.096 0 0.001001002 ( e ) (5 points) Convert the decimal number 0.75810 to an 8-bit binary number 0.758 x 2 1.516 1 x 2 1.032 1 x 2 0.064 0 x 2 0.128 0 x 2 0.256 0 x 2 0.512 0 x 2 1.024 1 x 2 0.096 0 0.110000102 ECE 15B Spring 2009 5 of 6 4. Timing Diagram (15 points) Using the following logic circuit: ( a ) (5 points) Derive a truth table for the output function (Z). A B C Z 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 ( b ) (10 points) Draw (using attached chart) the timing diagram of the circuit with respect to the initial conditions of the inputs and the gate delays given below: ( 1 ) A starts by being LOW (0) then at time = 2 nsec it goes HI (1). Then at time = 5 nsec, it goes LOW (It stays high for 3 nsec) ( 2 ) B is always on (Hi) ( 3 ) C starts by being HI (on). Then at time = 4 nsec, it goes low. At time = 6 nsec, it becomes HI again and remains that way for ever. ( 4 ) Assume the following gate delays: ( i ) AND gates have delays of 3 nsec ( ii ) OR gates have delays of 2 nsec ( iii ) INV gates have delays of 1 nsec SEE BELOW ( c ) (5 points) Identify any static or dynamic hazards, if any. NONE ECE 15B Spring 2009 (b) 0123 4 5 67 8 9 1011 12 13 14 15 16 17 18 nsec 6 of 6