Computer Design: Understanding Processing Units and Data Manipulation, Exams of Design

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Computer design – an application of digital logic design procedures
Computer = processing unit + memory system
Processing unit = control + datapath
Control = finite state machine  inputs = machine instruction, datapath conditions  outputs = register transfer control signals, ALU operation codes  instruction interpretation = instruction fetch, decode, execute
Datapath = functional units + registers  functional units = ALU, multipliers, dividers, etc.  registers = program counter, shifters, storage registers

   
 
      
     
 
    
    
         
           
Block diagram view
   
     

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Selectively loaded – EN or LD input
Output enable – OE input
Multiple registers – group 4 or 8 in parallel

      
Point-to-point connection  dedicated wires  muxes on inputs of each register
Common input from multiplexer  load enables for each register  control signals for multiplexer
Common bus with output enables  output enables and load enables for each register  2  2  2 3, 2  2   3, 4    3,

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Collections of registers in one package  two-dimensional array of FFs  address used as index to a particular word  can have separate read and write addresses so can do both at same time
4 by 4 register file  16 D-FFs  organized as four words of four bits each  write-enable (load)  read-enable (output enable)

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Larger collections of storage elements  implemented not as FFs but as much more efficient latches  high-density memories use 1 to 5 switches (transitors) per memory bit
Static RAM – 1024 words each 4 bits wide  once written, memory holds forever (not true for denser dynamic RAM)  address lines to select word (10 lines for 1024 words)  read enable
same as output enable
often called chip select
permits connection of many chips into larger array  write enable (same as load enable)  bi-directional data lines
output when reading, input when writing

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Example – an instruction to add the contents of two registers (Rx and Ry) and place result in a third register (Rz)
Step 1: get the ADD instruction from memory into an instruction register
Step 2: decode instruction  instruction in IR has the code of an ADD instruction  register indices used to generate output enables for registers Rx and Ry  register index used to generate load signal for register Rz
Step 3: execute instruction  enable Rx and Ry output and direct to ALU  setup ALU to perform ADD operation  direct result to Rz so that it can be loaded into register

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Data manipulation  add, subtract  increment, decrement  multiply  shift, rotate  immediate operands
Data staging  load/store data to/from memory  register-to-register move
Control  conditional/unconditional branches in program flow  subroutine call and return

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Standard FSM elements  state register  next-state logic  output logic (datapath/control signalling)  Moore or synchronous Mealy machine to avoid loops unbroken by FF
Plus additional "control" registers  instruction register (IR)  program counter (PC)
Inputs/outputs  outputs control elements of data path  inputs from data path used to alter flow of program (test if zero)

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Control state diagram (for each diagram)  reset  fetch instruction  decode  execute
Instructions partitioned into three classes  branch  load/store  register-to-register
Different sequence through diagram for each instruction type 9  
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Arithmetic circuits constructed in hierarchical and modular fashion  each bit in datapath is functionally identical  4-bit, 8-bit, 16-bit, 32-bit datapaths

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ALU block diagram  input: data and operation to perform  output: result of operation and status information

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Step 3

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Control  transfer data between registers by asserting appropriate control signals
Register transfer notation - work from register to register  instruction fetch: mabus ← PC; – move PC to memory address bus (PCmaEN, ALUmaEN) memory read; – assert memory read signal (mr, RegBmdEN) IR ← memory; – load IR from memory data bus (IRld) op ← add – send PC into A input, 1 into B input, add (srcA, srcB0, scrB1, op) PC ← ALUout – load result of incrementing in ALU into PC (PCld, PCsel)  instruction decode: IR to controller values of A and B read from register file (rs, rt)  instruction execution: op ← add – send regA into A input, regB into B input, add (srcA, srcB0, scrB1, op) rd ← ALUout – store result of add into destination register (regWrite, wrDataSel, wrRegSel)

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How many states are needed to accomplish these transfers?  data dependencies (where do values that are needed come from?)  resource conflicts (ALU, busses, etc.)
In our case, it takes three cycles  one for each step  all operation within a cycle occur between rising edges of the clock
How do we set all of the control signals to be output by the state machine?  depends on the type of machine (Mealy, Moore, synchronous Mealy)

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First pass at deriving the state diagram (Moore machine)  these will be further refined into sub-states  
  


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Assume Moore machine  outputs associated with states rather than arcs
Reset state and instruction fetch sequence
On reset (go to Fetch state)  start fetching instructions  PC will set itself to zero mabus ← PC; memory read; IR ← memory data bus; PC ← PC + 1;    
  
 


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Operation decode state  next state branch based on operation code in instruction  read two operands out of register file
what if the instruction doesn’t have two operands?  
  
 
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For add instruction  configure ALU and store result in register rd ← A + B  other instructions may require multiple cycles  
  
  

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Putting it all together and closing the loop  the famous instruction fetch decode execute cycle    
  
 
  
  
 
   
  
 

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Now we need to repeat this for all the instructions of our processor  fetch and decode states stay the same  different execution states for each instruction
some may require multiple states if available register transfer paths require sequencing of steps