Download Comp 411 Computer Organization: Problem Set #5 Solutions - Prof. Leona Mcmillan and more Assignments Computer Architecture and Organization in PDF only on Docsity! Comp 411 Computer Orginization Fall 2007 Problem Set #5 Solutions Problem 1 In the follows answers, the black section of the circuit is the new section, while the grey section is the section that was given in the problem. a) Vdd y A B C D A B C D A B C D y 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 1 b) Vdd y A B C D A B C D A B C D y 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 c) Vdd y A B C D A B C D A B C D y 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 2 b) After removing the inverter, the logic diagram appears as such: ? J K I Using similar elimination method as in a), it can be found the E is the only possible result. When using Y or Z as the selector to the mux and 0, Y, or Z as the input, many possible combinations can result in E. Here are two examples: Y Z 0 E E Y Y Z c) In a single level of CMOS logic, outputs of 1 can only be obtained if an input is 0 and outputs of 0 can only be obtained if an input is 1. Experimentation will show that only A can be implemented given the constraints. An example solutions is: Vdd Z X Y X Y Z A Note that an AND gate is two levels of CMOS logic: a CMOS NAND gate and a CMOS inverter. 5 d) Since the block E(X,Y,Z) simply outputs the appropriate value of E, the truth table for the circuit is as follows. U E B ? 0 0 ? 0 0 ? 0 0 ? 1 1 ? 0 1 ? 0 1 ? 0 1 ? 1 0 Since U and E are XORed together, the values for U must be: U E B 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 The input U must be tied to X, since E XOR X results in B. Problem 3 a) I will assume that the inputs are labeled from top to bottom, so I0 is the top input. A B 0 0 0 1 1 0 1 1 and or xor nand nor I0 0 0 0 1 1 I1 0 1 1 1 0 I2 0 1 1 1 0 I3 1 1 0 1 0 b) Yes, all 2-input Boolean functions can be implemented by inputing their truth tables to the logic block as the I inputs. 6 c) Valid answers are an enumeration of all 16 gate structures, or the NAND, NOR, and INVERT structures and a comment about reducibility. A few of the more difficult enumerations follow: B A B 1 0 XOR(A,B) A 0 B AND(A,B) A B NOR(A,B) 0 1 0 d) Let the 4 inputs be called A, B, C, and D. 3 of the inputs (A, B, and C) will be used as the selector to the 8-input mux. The actual input to the mux must now be considered. There are four possible inputs the mux: D, D, 0, 1. These values cover all possible outputs of a 4-input boolean function. The following table describes all possible combinations. A B C D Mux input Output Used as mux selector 0 D 01 1 0 D 1 1 0 0 0 01 0 0 1 11 1 e) This is similar to the case above, except that D is no longer available. There are 38 selections for the 8-input mux. One of the 4 inputs must be chosen to be used as the the input value to the mux. So, there are 38 ( 4 1 ) possible functions. There are a total of 216 4-input boolean functions. So, the upper bound is 38(41) 216 , or 38 214 functions. 7
