Computer System Overview: Understanding Operating Systems and Processors, Slides of Computer Science

Download Computer System Overview: Understanding Operating Systems and Processors and more Slides Computer Science in PDF only on Docsity! 1 Computer System Overview Chapter 1 Docsity.com 2 Operating System • Exploits the hardware resources of one or more processors • Provides a set of services to system users • Manages secondary memory and I/O devices Docsity.com 5 Top-Level Components PC MAR IR MBR I/O AR I/O BR CPU Main Memory System Bus I /O Module • • • • • • • • • Buffers Instruction 0 1 2 n - 2 n - 1 Data Data Data Data Instruction Instruction Figure 1.1 Computer Components: Top-Level View PC = Program counter I R = I nstruction register MAR = Memory address register MBR = Memory buffer register I /O AR = I nput/output address register I /O BR = I nput/output buffer register Execution unit Docsity.com 6 Processor Registers • User-visible registers – Enable programmer to minimize main- memory references by optimizing register use • Control and status registers – Used by processor to control operating of the processor – Used by privileged operating-system routines to control the execution of programs Docsity.com 7 User-Visible Registers • May be referenced by machine language • Available to all programs - application programs and system programs • Types of registers – Data – Address • Index • Segment pointer • Stack pointer Docsity.com 10 Control and Status Registers • Condition Codes or Flags – Bits set by the processor hardware as a result of operations – Examples • Positive result • Negative result • Zero • Overflow Docsity.com 11 Instruction Execution • Two steps – Processor reads instructions from memory • Fetches – Processor executes each instruction Docsity.com Instruction Cycle Fetch Stage Execute Stage Fetch Next Execute START Instruction: Instruction Figure 1.2 Basic Instruction Cycle HALT 12 Docsity.com Characteristics of a Hypothetical Machine 15 | Opcode [ Address | (a) Instruction format 0 1 15 | Ss | Magnitude (b) Integer format Program Counter (PC) = Address of instruction Instruction Register (IR) = Instruction being executed Accumulator (AC) = Temporary storage (c) Internal CPU registers 0001 = Load AC from Memory 0010 = Store AC to Memory 0101 = Add to AC from Memory (d) Partial list of opcodes Figure 1.3 Characteristics of a Hypothetical Machine 15 Docsity.com Example of Program Execution Memory CPU Registers | | Memory CPU Registers 300/194 0 Zo oPc | 301940 30 1|Pc 3201/5 a \ Ac} 301/59 4 1 000 3) ACI 42[2 9 4 1 19 4 QJIR 32/2 9 4 1 19 4 O}IR i i 940[0 0 0 3 o40(0 0 03 941[0 0 0 2 941[0 0 02) Step 1 Step 2 Memory CPU Registers | Memory CPU Registers 300/79 40 So ijrpc | 200 940 30 2) Pc 301/59 4 1 00 0 3) Ac} 301/5 9 41 05] Ac snfzoa| iss at 294 oo IR | 302 1 S947 i i 940 940 oo03 oo03 3+ s41[0 0 0 2 a1 [o-oa} Step 3 Step 4 Memory CPU Registers || Memory CPU Registers 300[1 9 40 Fogrc |s0Ts 4 703) Pc 3401/5 9 4 1 0 0 0 5) AC] 301/5 9 4 1 0 00:5) AC 30[2 94 1 294 1)IR| 302/29 41 294 1|IR T T i i 40/0 0.0 3 940/000 3 941[0 0 0 2 941,00 0 5 Step 5 Step 6 Figure 1.4 Example of Program Execution (contents of memory and registers in hexadecimal) 16 Docsity.com 17 Direct Memory Access (DMA) • I/O exchanges occur directly with memory • Processor grants I/O module authority to read from or write to memory • Relieves the processor responsibility for the exchange Docsity.com Program Flow of Control Without Interrupts User Program t¥ (a) No interrupts 20 Docsity.com 21 Program Flow of Control With Interrupts, Short I/O Wait User Program WRITE WRITE WRITE I/O Program I/O Command Interrupt Handler END 1 2a 2b 3a 3b 4 5 (b) Interrupts; short I/O wait Docsity.com 22 Program Flow of Control With Interrupts; Long I/O Wait Docsity.com Interrupt Cycle Fetch Stage Execute Stage Interrupt Stage Interrupts Disabled Interrupts Enabled HALT ) Figure 1.7 Instruction Cycle with Interrupts ‘Check for interrupt: initiate interrupt handler 25 Docsity.com 26 Interrupt Cycle • Processor checks for interrupts • If no interrupts fetch the next instruction for the current program • If an interrupt is pending, suspend execution of the current program, and execute the interrupt-handler routine Docsity.com Timing Diagram Based on Short 1/O Wait Time Processor vo lo @) vo operation Processor vo ® wait operation (b) With interrupts G) (circled numbers refer to numbers in Figure |.5b} (a) Without interrupts (circled numbers refer to numbers in Figure 1.5a) 27 Figure 1.8 Program Timing: Short I/O Wait . Docsity.com 30 Changes in Memory and Registers for an Interrupt Docsity.com 31 Changes in Memory and Registers for an Interrupt Docsity.com 32 Multiple Interrupts • Disable interrupts while an interrupt is being processed Docsity.com 35 Multiprogramming • Processor has more than one program to execute • The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O • After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt Docsity.com 36 Memory Hierarchy • Faster access time, greater cost per bit • Greater capacity, smaller cost per bit • Greater capacity, slower access speed Docsity.com Memory Hierarchy Figure 1.14 The Memory Hierarchy 37 Docsity.com 40 Disk Cache • A portion of main memory used as a buffer to temporarily to hold data for the disk • Disk writes are clustered • Some data written out may be referenced again. The data are retrieved rapidly from the software cache instead of slowly from disk Docsity.com 41 Cache Memory • Invisible to operating system • Increase the speed of memory • Processor speed is faster than memory speed • Exploit the principle of locality Docsity.com Cache Memory Block Transfer Word Transfer mA 4 Cache | Main Memory Figure 1.16 Cache and Main Memory 42 Docsity.com Cache Read Operation Receive address RA from CPU RA -read address Access main memory for block containing RA Fetch RA word and deliver to CPU Allocate cache slot for main memory block Deliver RA word to CPU Figure 1.18 Cache Read Operation 45 Docsity.com 46 Cache Design • Cache size – Small caches have a significant impact on performance • Block size – The unit of data exchanged between cache and main memory – Larger block size more hits until probability of using newly fetched data becomes less than the probability of reusing data that have to be moved out of cache Docsity.com 47 Cache Design • Mapping function – Determines which cache location the block will occupy • Replacement algorithm – Determines which block to replace – Least-Recently-Used (LRU) algorithm Docsity.com 50 Interrupt-Driven I/O • Processor is interrupted when I/O module ready to exchange data • Processor saves context of program executing and begins executing interrupt-handler • No needless waiting • Consumes a lot of processor time because every word read or written passes through the processor Docsity.com 51 Direct Memory Access • Transfers a block of data directly to or from memory • An interrupt is sent when the transfer is complete • Processor continues with other work Docsity.com