OS Lecture 2: Computer System Overview - Interrupts, Memory Hierarchy, Cache, Slides of Computer Science

Download OS Lecture 2: Computer System Overview - Interrupts, Memory Hierarchy, Cache and more Slides Computer Science in PDF only on Docsity! Operating Systems Lecture 02: Computer System Overview Docsity.com Today • Announcements: – Exam 2 time conflict with Algorithms – First HW posted: due midnight before next Th lecture • Finish chapter 1: – Interruptions – Memory Hierarchy – Cache – Symmetric Multiprocessors and Multicore – Direct Memory Access • Solution today’s jeopardy – Grade yourself and hand it to me Docsity.com Instruction Cycle With Interrupts Fetch Stage Execute Stage Interrupt Stage Interrupts Disabled Figure 1.7 Instruction Cycle with Interrupts iB 5 Docsity.com Program Timing: Short |/O Wait User Time ——_ oO oO @ @® a |.2. BD Jatin & & @ _ oo @ i Pe dt ® & @ (cuted munbes ie to numbers im Figure 1.5b) (a) Without interrupts (circled numbers refer to numbers in Figure 15a) Figure 1.8 Program Timing: Short I/O Wait Docsity.com Program Timing: Long I/O wait User 7“ ——— a Program @ @ @ _@ oo. —1_ Processor vo (2) = operation WRITE “ | operon ® a @ @ @ a ® L @ > WRITE | vo —__ Processor vo ‘operation wait operation Processor wait @ @ ® @ (etched numbers refer to numbers in Figure 1.5c) WRITE (a) Without interrupts (circled numbers refer to numbers in Figure 15a) c ; long iO wait (c) Interrupts 8 Figure 1.9 Program Timing: Long I/O Wait 7 Docsity.com Transfer of Control With Multiple Interrupts: Interrupt User Program Handler X Sequential Handler Y (a) Sequential interrupt processing Docsity.com Transfer of Control With Multiple Interrupts: Interrupt User Program Handler X Nested Interrupt Nested interrupt processing Docsity.com Example Time Sequence of Multiple Interrupts 12 I/O interrupts: a printer, a disk, and a communications line, with priorities of 2, 4, and 5, respectively. Docsity.com The Memory Hierarchy  Going down the hierarchy: decreasing cost per bit  increasing capacity  increasing access time decreasing frequency of access to the memory by the processor Docsity.com : – Memory references by the processor tend to cluster in time and space : – Data is organized so that the percentage of accesses to each successively lower level is substantially less than that of the level above – Can be applied across more than two levels of memory Docsity.com • Invisible to the processors, programmer, OS • Interacts with other memory management hardware • Reasons for its existence: – Processor must access memory at least once per instruction cycle – Processor execution is limited by memory cycle time – Exploit the principle of locality with a small, fast memory Docsity.com Cache/Main-Memory Structure Figure 1.17 Cache/Main-Memory Structure Docsity.com Cache Read Operation Figure 1.18 Cache Read Operation 3 Docsity.com CACHE DESIGN Main categories are: cache size block size mapping function replacement algorithm write policy number of cache levels Docsity.com Write Policy • can occur every time the block is updated • can occur when the block is replaced • minimizes write operations • leaves main memory in an obsolete state Dictates when the memory write operation takes place Docsity.com SMP AND MULTICORE Docsity.com Symmetric Multiprocessors (SMP) • A stand-alone computer system with the following characteristics: – two or more similar processors of comparable capability – processors share the same main memory and are interconnected by a bus or other internal connection scheme – processors share access to I/O devices – all processors can perform the same functions – the system is controlled by an integrated operating system that provides interaction between processors and their programs at the job, task, file, and data element levels Docsity.com Multicore Computer • Also known as a chip multiprocessor • Combines two or more processors (cores) on a single piece of silicon (die) • each core consists of all of the components of an independent processor • In addition, multicore chips also include L2 cache and in some cases L3 cache Docsity.com Intel Core i7 Supports two forms of external communications to other chips: DDR3 Memory Controller • brings the memory controller for the DDR (double data rate) main memory onto the chip • with the memory controller on the chip the Front Side Bus is eliminated QuickPath Interconnect (QPI) • enables high-speed communications among connected processor chips Docsity.com Intel Core i7 Figure 1.20 Intel Corei7 Block Diagram Docsity.com Programmed I/O • The I/O module performs the requested action then sets the appropriate bits in the I/O status register • The processor periodically checks the status of the I/O module until it determines the instruction is complete • With programmed I/O the performance level of the entire system is severely degraded Docsity.com Interrupt-Driven I/O Processor issues an I/O command to a module and then goes on to do some other useful work The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor The processor executes the data transfer and then resumes its former processing More efficient than Programmed I/O but still requires active intervention of the processor to transfer data between memory and an I/O module Docsity.com Interrupt-Driven I/O Drawbacks • Transfer rate is limited by the speed with which the processor can test and service a device • The processor is tied up in managing an I/O transfer  a number of instructions must be executed for each I/O transfer Docsity.com