Download Conditional Instructions and Predicated Operations in Pipelined Processors and more Slides Advanced Computer Architecture in PDF only on Docsity! Conditional Instructions Typical conditional instructions for pipeline processors are: Conditional Move – CMOVZ R1, R2, R3 it moves the value from one register to another if the condition is true; i.e., third operand – the predicate register R3 is Zero Such instructions are used to eliminate branch code sequence docsity.com Conditional Instructions Conditional ADD – (R8) ADD R1, R2, R3 assumes that the R1= R2+R3 occurs if the predicate register – R8 is 1 docsity.com Example 1 The code to implement this conditional statements can be written as: BNEZ R1, L ; No-op if A (R1)!= 0 ADDU R2, R3, R0 ; Else replace S (R2) by T (R3) L The IF statement can be implemented by the conditional move as: CMOVZ R2, R3, R1 Move R3 to R2 if the third operand R1=0 docsity.com Conditional or predicated Instructions Here, notice that using the Conditional instruction CMOVZ, the next operation is determined by the contents of the third register instead of condition evaluation i.e., the control dependence has been converted to data dependence docsity.com Conditional or predicated Instructions This transformation has moved the place to resolve dependence in a pipelined processor We know that, in a pipelined processor the dependence for branches is resolved near the front of the pipe Whereas, the conditional instruction resolve the dependence where the register-write occurs docsity.com Conditional or predicated Instructions Alternatively two CMPP instruction of the form: p1,p2 = CMPP.W. < UN. UC r1,r2 docsity.com Absolute Value Function: Example 2 Conditional move is also used to implement the absolute value function: A= abs (B) Which is implemented as: if B<0 {A=-B;} else {A=B;} Where this statement can be implemented as –pair of conditional moves CMOVZ R2, -R3, R1 CMOVZ R2, R3, R4 –or one unconditional move A=B and one conditional move A= - B docsity.com Conditional MOVE Instruction The Conditional moves enables us to eliminate the branch and improves the pipeline behavior It is useful for short sequences. It has certain limitations docsity.com Predicated LOAD Instructions Example Now let us consider another example code sequence for a two-issue superscalar The superscalar can issue a combination of one memory reference and one ALU operation or a branch by itself, every cycle. Let us see: docsity.com 2-Issue Instruction Code First instruction slot second instruction slot LW R1,40 R2) ADD R3,R4,R5 ADD R6,R3,R7 BEQZ R10,L LW R8,0R10) LW R9,0 R8) docsity.com
