Controller Design - Lecture Notes | ECEN 4517, Study notes of Electrical and Electronics Engineering

Download Controller Design - Lecture Notes | ECEN 4517 and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! version 10/28/98 10:09 AM Chapter 9 Controller Design 9 . 1 . Introduction In all switching converters, the output voltage v(t) is a function of the input line voltage vg(t), the duty cycle d(t), and the load current iload(t), as well as the converter circuit element values. In a dc-dc converter application, it is desired to obtain a constant output voltage v(t) = V , in spite of disturbances in vg(t) and iload(t), and in spite of variations in the converter circuit element values. The sources of these disturbances and variations are many, and a typical situation is illustrated in Fig. 9.1. The input voltage vg(t) of an off-line power supply may typically contain periodic variations at the second harmonic of the ac power system frequency (100Hz or 120Hz), produced by a rectifier circuit. The magnitude of vg(t) may also vary when neighboring power system loads are switched on or off. The load current iload(t) may contain variations of significant amplitude, and a typical power supply specification is that the output voltage must remain within a specified range (for example, 5V ±0.1V) when the load current takes a step change from, for example, full rated load current to 50% of the rated current, and vice-versa. The values of the circuit elements are a) + – + v(t) – vg(t) Switching converter Load pulse-width modulator vc(t) transistor gate driver δ(t) iload(t) δ(t) TsdTs t b) v(t) vg(t) iload(t) d(t) switching converter v(t) = f(vg, iload, d) disturbances control input } } Fig. 9.1. The output voltage of a typical switching converter is a function of the line input voltage vg, the duty cycle d, and the load current iload: (a) open- loop buck converter, (b) functional diagram illustrating dependence of v on the independent quantities vg, d, and iload. Chapter 9. Controller Design 2 constructed to a certain tolerance, and so in high-volume manufacturing of a converter, converters are constructed whose output voltages lie in some distribution. It is desired that essentially all of this distribution fall within the specified range; however, this is not practical to achieve without the use of negative feedback. Similar considerations apply to inverter applications, except that the output voltage is ac. So we cannot expect to simply set the dc-dc converter duty cycle to a single value, and obtain a given constant output voltage under all conditions. The idea behind the use of negative feedback is to build a circuit that automatically adjusts the duty cycle as necessary, to obtain the desired output voltage with high accuracy, regardless of disturbances in vg(t) or iload(t) or variations in component values. This is a useful thing to do whenever there are variations and unknowns that otherwise prevent the system from attaining the desired performance. A block diagram of a feedback system is shown in Fig. 9.2. The output voltage v(t) is measured, using a “sensor” with gain H(s). In a dc voltage regulator or dc-ac inverter, the sensor circuit is usually a voltage divider, comprised of precision resistors. The sensor output signal H(s)v(s) is compared with a reference input voltage vref(s). The objective is to a) + – + v – vg Switching converterPower input Load –+ compensator vref reference input Hvpulse-width modulator vc transistor gate driver δ Gc(s) H(s) ve error signal sensor gain iload b) vref reference input vcve(t) error signal sensor gain v(t) vg(t) iload(t) d(t) switching converter v(t) = f(vg, iload, d) disturbances control input } }+– pulse-widthmodulatorcompensator Fig. 9.2. Feedback loop for regulation of the output voltage: (a) buck converter, with feedback loop block diagram; (b) functional block diagram of the feedback system. Chapter 9. Controller Design 5 Zout(s) = – v(s) i load(s) d = 0 vg = 0 converter output impedance The Bode diagrams of these quantities are constructed in chapter 8. Equation (9-1) describes how disturbances vg and i load propagate to the output v , through the transfer function Gvg(s) and the output impedance Zout(s). If the disturbances vg and i load are known to have some maximum worst-case amplitude, then Eq. (9-1) can be used to compute the resulting worst-case open-loop variation in v . As described previously, the feedback loop of Fig. 9.2 can be used to reduce the influences of vg and i load on the output v . To analyze this system, let us perturb and linearize its averaged signals about their quiescent operating points. Both the power stage and the control block diagram are perturbed and linearized: vref(t) = Vref + vref(t) (9-2) ve(t) = Ve + ve(t) etc. In a dc regulator system, the reference input is constant, so vref(t) = 0. In a switching amplifier or dc-ac inverter, the reference input may contain an ac variation. In Fig. 9.4(a), the converter model of Fig. 9.3 is combined with the perturbed and linearized control circuit block diagram. This is equivalent to the reduced block diagram of Fig. 9.4(b), in which the converter model has been replaced by blocks representing Eq. (9-1). Solution of Fig. 9.4(b) for the output voltage variation v yields v = vref GcGvd / VM 1 + HGcGvd / VM + vg Gvg 1 + HGcGvd / VM – i load Zout 1 + HGcGvd / VM (9-3) which can be written in the form v = vref 1 H T 1 + T + vg Gvg 1 + T – i load Zout 1 + T (9-4) with T(s) = H(s)Gc(s)Gvd(s) / VM = “loop gain” Equation (9-4) is a general result. The loop gain T(s) is defined in general as the product of the gains around the forward and feedback paths of the loop. This equation shows how the addition of a feedback loop modifies the transfer functions and performance of the system, as described in detail below. Chapter 9. Controller Design 6 9.2.1. Feedback reduces the transfer functions from disturbances to the output The transfer function from vg to v in the open-loop buck converter of Fig. 9.3 is Gvg(s), as given in Eq. (9-1). When feedback is added, this transfer function becomes v(s) vg(s) vref = 0 i load = 0 = Gvg(s) 1 + T(s) (9-5) from Eq. (9-4). So this transfer function is reduced via feedback by the factor 1/(1+T(s)). If the loop gain T(s) is large in magnitude, then the reduction can be substantial. Hence, the output voltage variation v resulting from a given vg variation is attenuated by the feedback loop. a) + – +– 1 : M(D) Le C Rvg(s) + – v(s) e(s) d(s) j(s) d(s) i load(s) reference input error signal +– pulse-width modulator compensator d(s) ve(s) vc(s)vref(s) Gc(s) sensor gain H(s) 1 VM H(s) v(s) b) vg(s) v(s) i load(s) reference input error signal +– pulse-width modulatorcompensator d(s)ve(s) vc(s)vref(s) sensor gain H(s) 1 VM H(s) v(s) duty cycle variation Gc(s) Gvd(s) Gvg(s) Zout(s) ac line variation load current variation + –+ output voltage variation converter power stage Fig. 9.4. Voltage regulator system small-signal model: (a) with converter equivalent circuit; (b) complete block diagram. Chapter 9. Controller Design 7 Equation (9-4) also predicts that the converter output impedance is reduced, from Zout(s) to v(s) – i load(s) vref = 0 vg = 0 = Zout(s) 1 + T(s) (9-6) So the feedback loop also reduces the converter output impedance by a factor of 1/(1+T(s)), and the influence of load current variations on the output voltage is reduced. 9.2.2. Feedback causes the transfer function from the reference input to the output to be insensitive to variations in the gains in the forward path of the loop According to Eq. (9-4), the closed-loop transfer function from vref(t) to v is v(s) vref(s) vg = 0 i load = 0 = 1 H(s) T(s) 1 + T(s) (9-7) If the loop gain is large in magnitude, i.e., || T || >> 1, then (1+T) ≈ T and T/(1+T) ≈ T/T = 1. The transfer function then becomes v(s) vref(s) ≈ 1 H(s) (9-8) which is independent of Gc(s), VM, and Gvd(s). So provided that the loop gain is large in magnitude, then variations in Gc(s), VM, and Gvd(s) have negligible effect on the output voltage. Of course, in the dc regulator application, vref is constant and vref(t) = 0. But Eq. (9-8) applies equally well to the dc values. For example, if the system is linear, then we can write V Vref = 1 H(0) T(0) 1 + T(0) ≈ 1 H(0) (9-9) So to make the dc output voltage V accurately follow the dc reference Vref, we need only ensure that the dc sensor gain H(0) and dc reference Vref are well-known and accurate, and that T(0) is large. Precision resistors are normally used to realize H, but components with tightly-controlled values need not be used in Gc, the pulse-width modulator, or the power stage. The sensitivity of the output voltage to the gains in the forward path is reduced, while the sensitivity of v to the feedback gain H and the reference input vref is increased. Chapter 9. Controller Design 10 The asymptotes for the T(s) example of Fig. 9.5 are plotted in Fig. 9.7. At low frequencies where || T || is large, the disturbance transfer function from vg to v is v(s) vg(s) = Gvg(s) 1 + T(s) ≈ Gvg(s) T(s) (9-15) Again, Gvg(s) is the original transfer function, with no feedback. The closed-loop transfer function has magnitude reduced by the factor 1/|| T ||. So if, for example, we want to reduce this transfer function by a factor of 20 at 120Hz, then we need a loop gain || T || of at least 20 ⇒ 26dB at 120Hz. The disturbance transfer function from vg to v can be constructed on the graph, by multiplying the asymptotes of Fig. 9.7 by the asymptotes for Gvg(s). Similar arguments apply to the output impedance. The closed-loop output impedance at low frequencies is v(s) – i load(s) = Zout(s) 1 + T(s) ≈ Zout(s) T(s) (9-16) The output impedance is also reduced in magnitude by a factor of 1/|| T || at frequencies below the crossover frequency. At high frequencies (f > fc) where || T || is small, then 1/(1+T) ≈ 1, and v(s) vg(s) = Gvg(s) 1 + T(s) ≈ Gvg(s) v(s) – i load(s) = Zout(s) 1 + T(s) ≈ Zout(s) (9-17) fp1 QdB – 40dB/dec | T0 |dB fz fc fp2 – 20dB/dec – 40dB/dec crossover frequency || T || 0dB –20dB –40dB 20dB 40dB 60dB 80dB –60dB –80dB f 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz QdB – | T0 |dB + 40dB/dec + 20dB/dec fp1 fz 1 1 + T Fig. 9.7. Graphical construction of || 1 / (1 + T) ||. Chapter 9. Controller Design 11 This is the same as the original disturbance transfer function and output impedance. So the feedback loop has essentially no effect on the disturbance transfer functions at frequencies above the crossover frequency. 9 . 4 . Stability It is well known that adding a feedback loop can cause an otherwise stable system to become unstable. Even though the transfer functions of the original converter, Eq. (9-1), as well as of the loop gain T(s), contain no right half-plane poles, it is possible for the closed-loop transfer functions of Eq. (9-4) to contain right half-plane poles. The feedback loop then fails to regulate the system at the desired quiescent operating point, and oscillations are usually observed. It is important to avoid this situation. And even when the feedback system is stable, it is possible for the transient response to exhibit undesirable ringing and overshoot. The stability problem is discussed in this section, and a method for ensuring that the feedback system is stable and well-behaved is explained. When feedback destabilizes the system, the denominator (1+T(s)) terms in Eq. (9- 4) contain roots in the right half-plane (i.e., with positive real parts). If T(s) is a rational fraction, i.e., the ratio N(s)/D(s) of two polynomial functions N(s) and D(s), then we can write T(s) 1 + T(s) = N(s) D(s) 1 + N(s) D(s) = N(s) N(s) + D(s) 1 1 + T(s) = 1 1 + N(s) D(s) = D(s) N(s) + D(s) (9-18) So T(s)/(1+T(s)) and 1/(1+T(s)) contain the same poles, given by the roots of the polynomial (N(s) + D(s)). A brute-force test for stability is to evaluate (N(s) + D(s)), and factor the result to see whether any of the roots have positive real parts. However, for all but very simple loop gains, this involves a great deal of work. A simpler method is given by the Nyquist stability theorem, in which the number of right half-plane roots of (N(s) + D(s)) can be determined by testing T(s) [1,2]. This theorem is not discussed here. However, a special case of the theorem known as the phase margin test is sufficient for designing most voltage regulators, and is discussed in this section. 9.4.1. The phase margin test The crossover frequency fc is defined as the frequency where the magnitude of the loop gain is unity: Chapter 9. Controller Design 12 || T(j2πfc) || = 1 ⇒ 0dB (9-19) To compute the phase margin ϕm, the phase of the loop gain T is evaluated at the crossover frequency, and 180˚ is added. Hence, ϕm = 180˚ + ∠T(j2πfc) (9-20) If there is exactly one crossover frequency, and if the loop gain T(s) contains no right half- plane poles, then the quantities 1/(1+T) and T/(1+T) contain no right half-plane poles when the phase margin defined in Eq. (9-20) is positive. Thus, using a simple test on T(s), we can determine the stability of T/(1+T) and 1/(1+T). This is an easy-to-use design tool —we simple ensure that the phase of T is greater than –180˚ at the crossover frequency. When there are multiple crossover frequencies, the phase margin test may be ambiguous. Also, when T contains right half-plane poles (i.e., the original open-loop system is unstable), then the phase margin test cannot be used. In either case, the more general Nyquist stability theorem must be employed. The loop gain of a typical stable system is shown in Fig. 9.8. It can be seen that ∠T(j2πfc) = –112˚. Hence, ϕm = 180˚ – 112˚ = +68˚. Since the phase margin is positive, T/(1+T) and 1/(1+T) contain no right half- plane poles, and the feedback system is stable. The loop gain of an unstable system is sketched in Fig. 9.9. For this example, ∠T(j2πfc) = –230˚. The phase margin is ϕm = 180˚ – 230˚ = –50˚. The negative phase margin implies that T/(1+T) and 1/(1+T) each contain at least one right half-plane pole. fc crossover frequency 0dB –20dB –40dB 20dB 40dB 60dB f 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz fp1 fz || T || 0˚ –90˚ –180˚ –270˚ ϕm ∠ T ∠ T|| T || Fig. 9.8. Magnitude and phase of the loop gain of a stable system. The phase margin ϕm is positive. fc crossover frequency 0dB –20dB –40dB 20dB 40dB 60dB f 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz fp1 fp2 || T || 0˚ –90˚ –180˚ –270˚ ∠ T ∠ T|| T || ϕm (< 0) Fig. 9.9. Magnitude and phase of the loop gain of an unstable system. The phase margin ϕm is negative. Chapter 9. Controller Design 15 evaluate the exact phase of T at this frequency, and compute the phase margin. This phase margin is a function of the ratio f0/f2, or Q2. We can then solve to find Q as a function of the phase margin. The result is Q = cos ϕm sin ϕm ϕm = tan-1 1 + 1 + 4Q4 2Q4 (9-25) This function is plotted in Fig. 9.13, with Q expressed in dB. It can be seen that obtaining real poles (Q < 0.5) requires a phase margin of at least 76˚. To obtain Q = 1, a phase margin of 52˚ is needed. The system with a phase margin of 1˚ exhibits a closed-loop response with very high Q! With a small phase margin, T(jω) is very nearly equal to –1 in the vicinity of the crossover frequency. The denominator (1+T) then becomes very small, causing the closed-loop transfer functions to exhibit a peaked response at frequencies near the crossover frequency fc. Figure 9.13 is the result for the simple loop gain defined by Eq. (9-21). However, this loop gain is a good approximation for many other loop gains that are encountered in practice, in which || T || approaches unity gain with a –20dB/decade slope, with an additional pole at frequency f2. If all other poles and zeroes of T(s) are sufficiently far above or below the crossover frequency, then they have negligible effect on the system transfer functions near the crossover frequency, and Fig. 9.13 gives a good approximation for the relation between ϕm and Q. 0° 10° 20° 30° 40° 50° 60° 70° 80° 90° ϕm Q Q = 1 ⇒ 0dB Q = 0.5 ⇒ –6dB ϕm = 52˚ ϕm = 76˚ -20dB -15dB -10dB -5dB 0dB 5dB 10dB 15dB 20dB Fig. 9.13. Relation between loop gain phase margin ϕm and closed-loop peaking factor Q. Chapter 9. Controller Design 16 Another common case is the one in which || T || approaches unity gain with a –40dB/decade slope, with an additional zero at frequency f2. As f2 is increased, the phase margin is decreased and Q is increased. It can be shown that the relation between ϕm and Q is exactly the same, Eq. (9-25). A case where Fig. 9.13 fails is when the loop gain T(s) three or more poles at or near the crossover frequency. The closed-loop response then also contains three or more poles near the crossover frequency, and these poles cannot be completely characterized by a single Q-factor. Additional work is required to find the behavior of the exact T/(1+T) and 1/(1+T) near the crossover frequency, but nonetheless it can be said that a small phase margin leads to a peaked closed-loop response. 9.4.3. Transient response vs. damping factor One can solve for the unit-step response of the T/(1+T) transfer function, by multiplying Eq. (9-23) by 1/s and then taking the inverse Laplace transform. The result for Q > 0.5 is v(t) = 1 + 2Q e -ωct/2Q 4Q2 – 1 sin 4Q2 – 1 2Q ωc t + tan-1 4Q2 – 1 (9-26) For Q < 0.5, the result is v(t) = 1 – ω2ω2 – ω1 e –ω1t – ω1 ω1 – ω2 e –ω2t (9-27) with ω1, ω2 = ωc 2Q 1 ± 1 – 4Q2 These equations are plotted in Fig. 9.14 for various values of Q. According to Eq. (9- 23), when f2 > 4f0, the Q- factor is less than 0.5, and the closed-loop response contains a low-frequency and a high-frequency real pole. The transient response in this case, Eq. (9-27), contains decaying- exponential functions of time, of the form 0 0.5 1 1.5 2 0 5 10 15 ωct, radians v(t) Q=10 Q=50 Q=4 Q=2 Q=1 Q=0.75 Q=0.5 Q=0.3 Q=0.2 Q=0.1 Q=0.05 Q=0.01 Fig. 9.14. Unit-step response of the second-order system, Eqs. (9- 26) and (9-27), for various values of Q. Chapter 9. Controller Design 17 Ae (pole) t (9-28) This is called the “overdamped” case. With very low Q, the low-frequency pole leads to a slow step response. For f2 = 4f0, the Q-factor is equal to 0.5. The closed-loop response contains two real poles at frequency 2f0. This is called the “critically damped” case. The transient response is faster than in the overdamped case, because the lowest-frequency pole is at a higher frequency. This is the fastest response that does not exhibit overshoot. At ωct = π radians (t = 1/2fc), the voltage has reached 82% of its final value. At ωct = 2π radians (t = 1/fc), the voltage has reached 98.6% of its final value. For f2 < 4f0, the Q-factor is greater than 0.5. The closed-loop response contains complex poles, and the transient response exhibits sinusoidal-type waveforms with decaying amplitude, Eq. (9-26). The rise time of the step response is faster than in the critically-damped case, but the waveforms exhibit overshoot. The peak value of v(t) is peak v(t) = 1 + e– π / 4Q 2 – 1 (9-29) This is called the “underdamped” case. A Q-factor of 1 leads to an overshoot of 16.3%, while a Q-factor of 2 leads to a 44.4% overshoot. Large Q-factors lead to overshoots approaching 100%. The exact transient response of the feedback loop may differ from the plots of Fig. 9.14, because of additional poles and zeroes in T, and because of differences in initial conditions. Nonetheless, Fig. 9.14 illustrates how high-Q poles lead to overshoot and ringing. In most power applications, overshoot is unacceptable. For example, in a 5V computer power supply, the voltage must not be allowed to overshoot to 7 or 10 volts when the supply is turned on —this would destroy all of the TTL integrated circuits in the computer! So the Q-factor must be sufficiently low, often 0.5 or less, corresponding to a phase margin of at least 76˚. 9 . 5 . Regulator design Let’s now consider how to design a regulator system, to meet specifications or design goals regarding rejection of disturbances, transient response, and stability. Typical dc regulator designs are defined using specifications such as the following: (1) Effect of load current variations on the output voltage regulation. The output voltage must remain within a specified range when the load current varies in a prescribed way. This amounts to a limit on the maximum magnitude of the closed-loop output impedance of Eq. (9-6), repeated below Chapter 9. Controller Design 20 The maximum phase occurs at a frequency fϕmax given by the geometrical mean of the pole and zero frequencies: fϕmax = fz fp (9-33) To obtain the maximum improvement in phase margin, we should design our compensator so that the frequency fϕmax coincides with the loop gain crossover frequency fc. The value of the phase at this frequency can be shown to be ∠ Gc( fϕmax) = tan-1 fp fz – fz fp 2 (9-34) This equation is plotted in Fig. 9.16. Equation (9-34) can be inverted to obtain fp fz = 1 + sin θ 1 – sin θ (9-35) where θ = ∠Gc(fϕmax). Equations (9-34) and (9-32) imply that, to optimally obtain a compensator phase lead of θ at frequency fc, the pole and zero frequencies should be chosen as follows: fz = fc 1 – sin θ 1 + sin θ fp = fc 1 + sin θ 1 – sin θ (9-36) When it is desired to avoid changing the crossover frequency, the magnitude of the compensator gain is chosen to be unity at the loop gain crossover frequency fc. This requires that Gc0 be chosen according to the following formula: Gc0 = fz fp (9-37) It can be seen that Gc0 is less than unity, and therefore the lead compensator reduces the dc gain of the feedback loop. Other choices of Gc0 can be selected when it is desired to shift the crossover frequency fc; for example, increasing the value of Gc0 causes the crossover frequency to increase. If the frequencies fp and fz are chosen as in Eq. (9-36), then fϕmax of Eq. (9-32) will coincide with the new crossover frequency fc. 1 10 100 1000 maximum phase lead 0˚ 15˚ 30˚ 45˚ 60˚ 75˚ 90˚ fp / fz Fig. 9.16. Maximum phase lead θ vs. frequency ratio fp / fz for the lead compensator. Chapter 9. Controller Design 21 The Bode diagram of a typical loop gain T(s) containing two poles is illustrated in Fig. 9.17. The phase margin of the original T(s) is small, since the crossover frequency fc is substantially greater than the pole frequency f0. The result of adding a lead compensator is also illustrated. The lead compensator of this example is designed to maintain the same crossover frequency but improve the phase margin. 9.5.2. Lag (PI) compensator This type of compensator is used to increase the low-frequency loop gain, such that the output is better regulated at dc and at frequencies well below the loop crossover frequency. As given in Eq. (9-38) and illustrated in Fig. 9.18, an inverted zero is added to the loop gain, at frequency fL. Gc(s) = Gc∞ 1 + ωL s (9-38) If fL is sufficiently lower than the loop crossover frequency fc, then the phase margin is unchanged. This type of compensator is also called a proportional-plus-integral, or PI, controller —at low frequencies, the inverted zero causes the compensator to integrate the error signal. To the extent that the compensator gain can be made arbitrarily large at dc, the dc loop gain T(0) becomes arbitrarily large. This causes the dc component of the error signal to approach zero. In consequence, the steady-state output voltage is perfectly regulated, and the disturbance-to-output transfer functions approach zero at dc. Such behavior is easily f || T || 0˚ –90˚ –180˚ –270˚ ∠ T || T || ∠ T T0 f0 0˚ fz fp fc ϕm T0 Gc0 original gain compensated gain original phase asymptotes compensated phase asymptotes 0dB –20dB –40dB 20dB 40dB 60dB Fig. 9.17. Compensation of a loop gain containing two poles, using a lead (PD) compensator. The phase margin ϕm is improved. f || Gc || ∠ Gc Gc∞ 0˚ fL/10 + 45˚/decade fL – 90˚ 10fL – 20dB /decade Fig. 9.18. Magnitude and phase asymptotes of the PI compensator transfer function Gc of Eq. (9-38). Chapter 9. Controller Design 22 obtained in practice, with the compensator of Eq. (9-38) realized using a conventional operational amplifier. Although the PI compensator is useful in nearly all types of feedback systems, it is an especially simple and effective approach for systems originally containing a single pole. For the example of Fig. 9.19, the original uncompensated loop gain is of the form Tu(s) = Tu0 1 + sω0 (9-39) The compensator transfer function of Eq. (9-38) is used, so that the compensated loop gain is T(s) = Tu(s) Gc(s). Magnitude and phase asymptotes of T(s) are also illustrated in Fig. 9.19. The compensator high-frequency gain Gc∞ is chosen to obtain the desired crossover frequency fc. If we approximate the compensated loop gain by its high-frequency asymptote, then at high frequencies we can write T ≈ Tu0Gc∞ f f0 (9-40) At the crossover frequency f = fc, the loop gain has unity magnitude. Equation (9-40) predicts that the crossover frequency is fc ≈ Tu0Gc∞ f0 (9-41) Hence, to obtain a desired crossover frequency fc, we should choose the compensator gain Gc∞ as follows: Gc∞ = fc Tu0 f0 (9-42) The corner frequency fL is then chosen to be sufficiently less than fc, such that an adequate phase margin is maintained. Magnitude asymptotes of the quantity 1 / (1 + T(s)) are constructed in Fig. 9.20. At frequencies less than fL, the PI compensator improves the rejection of disturbances. At dc, 0dB –20dB –40dB 20dB 40dB f 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz 90˚ 0˚ –90˚ –180˚ Gc∞Tu0 fL f0 Tu0 ∠ Tu || Tu || f0 || T || fc ∠ T 10 fL 10 f0 ϕm Fig. 9.19. Compensation of a loop gain containing a single pole, using a lag (PI) compensator. The loop gain magnitude is increased. Chapter 9. Controller Design 25 in the load current are modeled. For generality, reference voltage variations vref are included in the diagram; in a dc voltage regulator, these variations are normally zero. The open-loop converter transfer functions are discussed in the previous chapters. The open-loop control-to-output transfer function is Gvd(s) = V D 1 1 + s LR + s 2LC (9-47) The open-loop control-to-output transfer function contains two poles, and can be written in the following normalized form: Gvd(s) = Gd0 1 1 + s Q0ω0 + sω0 2 (9-48) By equating like coefficients in Eqs. (9-47) and (9-48), one finds that the dc gain, corner frequency, and Q-factor are given by Gd0 = VD = 28V f0 = ω0 2π = 1 2π LC = 1kHz Q0 = R C L = 9.5 ⇒ 19.5dB (9-49) In practice, parasitic loss elements, such as the capacitor equivalent series resistance (esr), would cause a lower Q-factor to be observed. Figure 9.24 contains a Bode diagram of Gvd(s). The open-loop line-to-output transfer function is Gvg(s) = D 1 1 + s LR + s 2LC (9-50) This transfer function contains the same poles as in Gvd(s), and can be written in the normalized form + – +– 1 : D L C Rvg(s) + – v(s) V D2 d V R d iload(s) error signal +– compensator d(s) ve(s) vc(s)vref ( = 0) Gc(s) H(s) 1 VM H(s) v(s) T(s) VM = 4V H = 1 3 Fig. 9.23. System small-signal ac model, design example. Chapter 9. Controller Design 26 Gvg(s) = Gg0 1 1 + s Q0ω0 + sω0 2 (9-51) with Gg0 = D. The open-loop output impedance of the buck converter is Zout(s) = R || 1 sC || sL = sL 1 + s LR + s 2LC (9-52) Use of these equations to represent the converter in block-diagram form leads to the complete system block diagram of Fig. 9.25. The loop gain of the system is T(s) = Gc(s) 1 VM Gvd(s) H(s) (9-53) Substitution of Eq. (9-48) into (9-53) leads to T(s) = Gc(s) H(s) VM V D 1 1 + s Q0ω0 + sω0 2 (9-54) f 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz 0˚ –90˚ –180˚ –270˚ ∠ Gvd f0 || Gvd || Gd0 = 28V ⇒ 29dBV || Gvd || ∠ Gvd 0dBV –20dBV –40dBV 20dBV 40dBV 60dBV Q0 = 9.5 ⇒ 19.5dB 10–1 / 2Q0 f0 = 900Hz 101 / 2Q0 f0 = 1.1kHz Fig. 9.24. Converter small-signal control-to-output transfer function Gvd, design example. vg(s) v(s) i load(s) +– d(s)ve(s) vc(s)vref ( = 0) H(s) 1 VM duty cycle variation Gc(s) Gvd(s) Gvg(s) Zout(s) ac line variation load current variation + –+ converter power stage T(s) VM = 4V H = 1 3 Fig. 9.25. System block diagram, design example. Chapter 9. Controller Design 27 The closed-loop disturbance-to-output transfer functions are given by Eqs. (9-5) and (9-6). The uncompensated loop gain Tu(s), with unity compensator gain, is sketched in Fig. 9.26. With Gc(s) = 1, Eq. (9-54) can be written Tu(s) = Tu0 1 1 + s Q0ω0 + sω0 2 (9-55) where the dc gain is Tu0 = H VD VM = 2.33 ⇒ 7.4dB (9-56) The uncompensated loop gain has a crossover frequency of approximately 1.8kHz, with a phase margin of less than five degrees. Let us design a compensator, to attain a crossover frequency of fc = 5kHz, or one twentieth of the switching frequency. From Fig. 9.26, the uncompensated loop gain has a magnitude at 5kHz of approximately Tu0 (f0 / fc) 2 = 0.093 ⇒ –20.6dB. So to obtain unity loop gain at 5kHz, our compensator should have a 5kHz gain of +20.6dB. In addition, the compensator should improve the phase margin, since the phase of the uncompensated loop gain is nearly –180˚ at 5kHz. So a lead (PD) compensator is needed. Let us (somewhat arbitrarily) choose to design for a phase margin of 52˚. According to Fig. 9.13, this choice leads to closed-loop poles having a Q-factor of 1. The unit step response, Fig. 9.14, then exhibits a peak overshoot of 16%. Evaluation of Eq. (9-36), with fc = 5kHz and θ = 52˚, leads to the following compensator pole and zero frequencies: fz = (5kHz) 1 – sin (52°) 1 + sin (52°) = 1.7kHz fp = (5kHz) 1 + sin (52°) 1 – sin (52°) = 14.5kHz (9-57) To obtain a compensator gain of 20.6dB ⇒ 10.7 at 5kHz, the low-frequency compensator gain must be 0dB –20dB –40dB 20dB 40dB f 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz || Tu || 0˚ –90˚ –180˚ –270˚ ∠ Tu || Tu || ∠ Tu Tu0 2.33 ⇒ 7.4dB f0 1kHz 0˚ 10 – 12Q f0 = 900Hz 10 1 2Q f0 = 1.1kHz Q0 = 9.5 ⇒ 19.5dB – 40 dB/decade Fig. 9.26. Uncompensated loop gain Tu, design example. Chapter 9. Controller Design 30 phase margin, let us (somewhat arbitrarily) choose fL to be one-tenth of the crossover frequency, or 500Hz. The inverted zero will then increase the loop gain at frequencies below 500Hz, improving the low- frequency regulation of the output voltage. The loop gain of Fig. 9.31 is obtained. The magnitude of the quantity 1 / (1 + T) is also constructed. It can be seen that the inverted zero at 500Hz causes the magnitude of 1 / (1 + T) at 100Hz to be reduced by a factor of approximately (100Hz) / (500Hz) = 1/5. The total attenuation of 1 / (1 + T) at 100Hz is -32.7dB. A 1V, 100Hz variation in vg(t) would now induce a 12mV variation in v(t). Further improvements could be obtained by increasing fL; however, this would require redesign of the PD portion of the compensator to maintain an adequate phase margin. The line-to-output transfer function is constructed in Fig. 9.32. Both the open-loop transfer function Gvg(s), Eq. (9-51), and the closed-loop transfer function Gvg(s) / (1 + T(s)), are constructed using the algebra-on-the-graph method. The two transfer functions coincide at frequencies greater than the crossover frequency. At frequencies less than the crossover frequency fc, the closed-loop transfer function is reduced by a factor of T(s). It can be seen that the poles of Gvg(s) are cancelled by zeroes of 1 / (1 + T). Hence the closed- loop line-to-output transfer function is approximately f 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz || T || f0 fz fp fc Q01 1 + T fL Q0 0dB –20dB –40dB 20dB 40dB 60dB –60dB –80dB Fig. 9.31. Construction of || T || and || 1 / (1 + T) || with the PID-compensator of Fig. 9.30. D Tu0Gcm f 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz fz fc fL v vg open-loop || Gvg || closed-loop Gvg 1 + T –40dB –60dB –80dB –20dB 0dB 20dB –100dB f0 Q0Gvg(0) = D – 40dB/dec 20dB/dec Fig. 9.32. Comparison of open-loop line-to-output transfer function Gvg and closed-loop line-to-output transfer function of Eq. (9- 61). Chapter 9. Controller Design 31 Gvg(s) 1 + T(s) ≈ D Tu0 Gcm 1 1 + ωL s 1 + s ωz 1 + s ωc (9-61) So the algebra-on-the-graph method allows simple approximate disturbance-to-output closed-loop transfer functions to be written. Armed with such an analytical expression, the system designer can easily compute the output disturbances, and can gain the insight required to modify the element values such that system specifications are met. 9 . 6 . Measurement of loop gains It is good engineering practice to measure the loop gains of prototype feedback systems. The objective of such an exercise is to verify that the system has been correctly modeled. If so, then provided that a good controller design has been implemented, then the system behavior will meet expectations regarding transient overshoot (and phase margin), rejection of disturbances, dc output voltage regulation, etc. Unfortunately, there are reasons why practical system prototypes are likely to differ from theoretical models. Phenomena may occur which were not accounted for in the original model, and which significantly influence the system behavior. Noise and EMI can be present, which cause the system transfer functions to deviate in unexpected ways. So let us consider the measurement of the loop gain T(s) of the feedback system of Fig. 9.33. We will make measurements at some point A, where two blocks of the network are connected electrically. In Fig. 9.33, the output port of block 1 is represented by a Thevenin-equivalent network, composed of the dependent voltage source G1ve and output impedance Z1. Block 1 is loaded by the input impedance Z2 of block 2. The remainder of the feedback system is represented by a block diagram as shown. The loop gain of the system is G2(s) vx(s) = v(s)+– ve(s)vref(s) H(s) + – Z1(s) Z2(s) A + – vx(s)G1(s) ve(s) T(s) Block 1 Block 2 Fig. 9.33. It is desired to determine the loop gain T(s) experimentally, by making measurements at point A. Chapter 9. Controller Design 32 T(s) = G1(s) Z2(s) Z1(s) + Z2(s) G2(s) H(s) (9-62) Measurement of this loop gain presents several challenges not present in other frequency response measurements. G2(s) vx(s) = v(s)+– ve(s)vref(s) H(s) + – Z1(s) Z2(s) + – vx(s)G1(s) ve(s) Block 1 Block 2 – + vy(s) vz dc bias VCC 0 Tm(s) Fig. 9.34. Measurement of loop gain by breaking the loop. In principle, one could break the loop at point A, and attempt to measure T(s) using the transfer function measurement method of the previous chapter. As illustrated in Fig. 9.34, a dc supply voltageVCC and potentiometer would be used, to establish a dc bias in the voltage vx, such that all of the elements of the network operate at the correct quiescent point. Ac voltage variations in vz(t) are coupled into the injection point via a dc blocking capacitor. Any other independent ac inputs to the system are disabled. A network analyzer is used to measure the relative magnitudes and phases of the ac components of the voltages vy(t) and vx(t): Tm(s) = vy(s) vx(s) vref = 0 vg = 0 (9-63) The measured gain Tm(s) differs from the actual gain T(s) because, by breaking the connection between blocks 1 and 2 at the measurement point, we have removed the loading of block 2 on block 1. Solution of Fig. 9.34 for the measured gain Tm(s) leads to Tm(s) = G1(s) G2(s) H(s) (9-64) Equations (9-62) and (9-64) can be combined to express Tm(s) in terms of T(s): Tm(s) = T(s) 1 + Z1(s) Z2(s) (9-65) Hence, Tm(s) ≈ T(s) provided that Z2 >> Z1 (9-66) Chapter 9. Controller Design 35 with the voltage injection technique. If Z1 / Z2 is much smaller in magnitude than T(s), then the second term can be ignored, and Tv(s) ≈ T(s). At frequencies where T(s) is smaller in magnitude than Z1 / Z2, the measured data must be discarded. Thus, Tv(s) ≈ T(s) provided (i) Z1(s) << Z2(s) , and (ii) T(s) >> Z1(s) Z2(s) (9-75) Again, note that the value of the injection source impedance Zs is irrelevant. As an example, consider voltage injection at the output of an operational amplifier, having a 50Ω output impedance, which drives a 500Ω effective load. The system in the vicinity of the injection point is illustrated in Fig. 9.36. So Z1(s) = 50Ω and Z2(s) = 500Ω. The ratio Z1 / Z2 is 0.1, or –20dB. Let us further suppose that the actual loop gain T(s) contains poles at 10Hz and 100kHz, with a dc gain of 80dB. The actual loop gain magnitude is illustrated in Fig. 9.37. Voltage injection would result in measurement of Tv(s) given in Eq. (9-74). Note that 1 + Z1(s) Z2(s) = 1.1 ⇒ 0.83dB (9-76) Hence, for large || T ||, the measured || Tv || deviates from the actual loop gain by less than 1dB. However, at high frequency where || T || is less than –20dB, the measured gain differs significantly. Apparently, Tv(s) contains two high-frequency zeroes that are not present in T(s). Depending on the Q-factor of these zeroes, the phase of Tv at the crossover frequency could be influenced. To ensure that the phase – + + – + – +– 50Ω 500Ω vz vx(s)vy(s) Block 1 Block 2 Fig. 9.36. Voltage injection example. f || T || 0dB –20dB –40dB 20dB 40dB 60dB 80dB 100dB 10Hz 100Hz 1kHz 10kHz 100kHz 1MHz || Tv || Z1 Z2 ⇒ – 20dB || Tv || || T || Fig. 9.37. Comparison of measured loop gain Tv and actual loop gain T, voltage injection example. The measured gain deviates at high frequency. Chapter 9. Controller Design 36 margin is correctly measured, it is important that Z 1 / Z 2 be sufficiently small in magnitude. 9.6.2. Current injection The results of the preceding paragraphs can also be obtained in dual form, where the loop gain is measured by current injection [3]. As illustrated in Fig. 9.38, we can model block 1 and the analyzer injection source by their Norton equivalents, and use current probes to measure îx and îy. The gain measured by current injection is Ti(s) = i y(s) i x(s) vref = 0 vg = 0 (9-77) It can be shown that Ti(s) = T(s) 1 + Z2(s) Z1(s) + Z2(s) Z1(s) (9-78) Hence, Ti(s) ≈ T(s) provided (i) Z2(s) << Z1(s) , and (ii) T(s) >> Z2(s) Z1(s) (9-79) So to obtain an accurate measurement of the loop gain by current injection, we must find a point in the network where block 2 has sufficiently small input impedance. Again, note that the injection source impedance Zs does not affect the measurement. In fact, we can realize îz by use of a Thevenin-equivalent source, as illustrated in Fig. 9.39. The network analyzer injection source is represented G2(s) vx(s) = v(s)+– ve(s)vref(s) H(s) + – Z2(s)G1(s) ve(s) Block 1 Block 2 0 Ti(s) Z1(s) i xi y i z Zs(s) Fig. 9.38. Measurement of loop gain by current injection. vz Rs Cb i xi y i z Fig. 9.39. Current injection using Thevenin- equivalent source. Chapter 9. Controller Design 37 by voltage source vz and output resistance Rs. A series capacitor, Cb, is inserted to avoid disrupting the dc bias at the injection point. 9.6.3. Measurement of unstable systems When the prototype feedback system is unstable, we are even more eager to measure the loop gain —to find out what went wrong. But measurements cannot be made while the system oscillates. We need to stabilize the system, yet measure the original unstable loop gain. It is possible to do this by recognizing that the injection source impedance Zs does not influence the measured loop gain [3]. As illustrated in Fig. 9.40, we can even add additional resistance Rext, effectively increasing the source impedance Zs. The measured loop gain Tv(s) is unaffected. – + G2(s) vx(s) = v(s)+– ve(s)vref(s) H(s) + – Z2(s)G1(s) ve(s) Block 1 Block 2 vy(s) 0 Tv(s) Z1(s) + – vx(s) Rext – +vz Lext Zs(s) Fig. 9.40. Measurement of an unstable loop gain by voltage injection. Adding series impedance generally lowers the loop gain of a system, leading to a lower crossover frequency and a more positive phase margin. Hence, it is usually possible to add a resistor Rext that is sufficiently large to stabilize the system. The gain Tv(s), Eq. (9- 67), continues to be approximately equal to the original unstable loop gain, according to Eq. (9-75). To avoid disturbing the dc bias conditions, it may be necessary to bypass Rext with inductor Lext. If the inductance value is sufficiently large, then it will not influence the stability of the modified system. 9 . 7 . Summary of key points 1. Negative feedback causes the system output to closely follow the reference input, according to the gain 1 / H(s). The influence on the output of disturbances and variation of gains in the forward path is reduced. 2. The loop gain T(s) is equal to the products of the gains in the forward and feedback paths. The loop gain is a measure of how well the feedback system works: a large loop gain leads to better regulation of the output. The crossover frequency fc is the Chapter 9. Controller Design 40 where T0 = 100 ω1 = 500 rad/s ω2 = 1000 rad/s ω3 = 24000 rad/s ωz = 4000 rad/s Gg0 = 0.5 The gain of the feedback connection is H(s) = 0.1. (a) Sketch the magnitude and phase asymptotes of the loop gain T(s). Determine numerical values of the crossover frequency in Hz and phase margin in degrees. (b) Construct the magnitude asymptotes of the closed-loop line-to-output transfer function. Label important features. (c) Construct the magnitude asymptotes of the closed-loop transfer function from the reference voltage to the output voltage. Label important features. 9 . 5 . The forward converter system of Fig. 9.43 is constructed with the element values shown. The quiescent value of the input voltage is Vg = 380V. The transformer has turns ratio n1 / n3 = 4.5. The duty cycle produced by the pulse-width modulator is restricted to the range 0 ≤ d(t) ≤ 0.5. Within this range, d(t) follows the control voltage vc(t) according to d(t) = 1 2 vc(t) VM with VM = 3 volts. (a) Determine the quiescent values of: the duty cycle D, the output voltage V , and the control voltage Vc. (b) Sketch a block diagram which models the small- signal ac variations in the system, and determine the transfer function of each block. (c) Construct a Bode plot of the loop gain magnitude and phase. What is the crossover frequency? What is the phase margin? (d) Construct the Bode plot of the closed-loop line-to-output transfer function magnitude v vg Label important features. What is the gain at 120Hz? At what frequency do disturbances in vg have the greatest influence on the output voltage? 9 . 6 . In the voltage regulator system of Fig. 9.43, described in problem 9.5, the input voltage vg(t) contains a 120Hz variation of peak amplitude 10V. (a) What is the amplitude of the resulting 120Hz variation in v(t)? + – n1 : n1 : n3 C R + v(t) – L vg(t) vref pulse-width modulator vc isolated transistor gate driver fs = 150kHz 500µH 10µF 7Ω T(s) 5.1V + – 13nF 5.6kΩ 81.8kΩ 18.2kΩ Fig. 9.43. Chapter 9. Controller Design 41 (b) Modify the compensator network such that the 120Hz output voltage variation has peak amplitude less than 25mV. Your modification should leave the dc output voltage unchanged, and should result in a crossover frequency no greater than 10kHz. 9 . 7 . Design of a boost converter with current feedback and a PI compensator. In some applications, it is desired to control the converter terminal current waveform. The boost converter system of Fig. 9.44 contains a feedback loop which causes the converter input current ig(t) to be proportional to a reference voltage vref(t). The feedback connection is a current sense circuit having gain H(s) = 0.2 volts per ampere. A conventional pulse width modulator circuit (Fig. 7.62) is employed, having a sawtooth waveform with peak-peak amplitude of VM = 3 volts. The quiescent values of the inputs are: Vg = 120 volts, Vref = 2 volts. All elements are ideal. (a) Determine the quiescent values D, V, and Ig. (b) Determine the small-signal transfer function Gid(s) = ig(s) d(s) (c) Sketch the magnitude and phase asymptotes of the uncompensated (Gc(s) = 1) loop gain. (d) It is desired to obtain a loop gain magnitude of at least 35dB at 120Hz, while maintaining a phase margin of at least 72˚. The crossover frequency should be no greater than fs / 10 = 10kHz. Design a PI compensator which accomplishes this. Sketch the magnitude and phase asymptotes of the resulting loop gain, and label important features. (e) For your design of part (d), sketch the magnitude of the closed-loop transfer function ig(s) vref(s) Label important features. 9 . 8 . Design of a buck regulator to meet closed-loop output impedance specifications. The buck converter with control system illustrated in Fig. 9.45 is to be designed to meet the following specifications. The closed-loop output impedance should be less than 0.2Ω over the entire frequency range 0-20kHz. To ensure that the transient response is well-behaved, the poles of the closed- loop transfer functions, in the vicinity of the crossover frequency, should have Q-factors no greater than unity. The quiescent load current ILOAD can vary from 5A to 50A, and the above specifications must be met for every value of ILOAD in this range. For simplicity, you may assume that the + – + v – vg –+ compensator vref reference input pulse-width modulator vc transistor gate driver δ Gc(s) H(s) ve fs = 100kHz L C R ig 400µH 10µF 120Ω T(s) VM = 3V ig H(s) ig(s) Fig. 9.44. + – + v – vg –+ compensator vref Hvpulse-width modulator vc transistor gate driver δ Gc(s) H(s) ve H(s) = 0.1fs = 100kHz L 1mH C 200µF VM = 4V 5V iload Rload Zout 100V Fig. 9.45. Chapter 9. Controller Design 42 input voltage vg does not vary. The loop gain crossover frequency fc may be chosen to be no greater than fs / 10, or 10kHz. You may also assume that all elements are ideal. The pulse-width modulator circuit obeys Eq. (7-132). (a) What is the intended dc output voltage V? Over what range does the effective load resistance RLOAD vary? (b) Construct the magnitude asymptotes of the open-loop output impedance Zout(s). Over what range of frequencies is the output impedance specification not met? Hence, deduce how large the minimum loop gain T(s) must be in magnitude, such that the closed-loop output impedance meets the specification. Choose a suitable crossover frequency fc. (c) Design a compensator network Gc(s) such that all specifications are met. Additionally, the dc loop gain T(s) should be at least 20dB. Specify the following: (i) Your choice for the transfer function Gc(s) (ii) The worst-case closed-loop Q (iii) Bode plots of the loop gain T(s) and the closed-loop output impedance, for load currents of 5A and 50A. What effect does variation of RLOAD have on the closed-loop behavior of your design? (d) Design a circuit using resistors, capacitors, and an op amp, to realize your compensator transfer function Gc(s). 9 . 9 Design of a buck-boost voltage regulator. The buck-boost converter of Fig. 9.46 operates in the continuous conduction mode, with the element values shown. The nominal input voltage is Vg = 48V, and it is desired to regulate the output voltage at –15V. Design the best compensator that you can, which has high crossover frequency (but no greater than 10% of the switching frequency), large loop gain over the bandwidth of the feedback loop, and phase margin of at least 52˚. (a) Specify the required value of H. Sketch Bode plots of the uncompensated loop gain magnitude and phase, as well as the magnitude and phase of your proposed compensator transfer function Gc(s). Label the important features of your plots. (b) Construct Bode diagrams of the magnitude and phase of your compensated loop gain T(s), and also of the magnitude of the quantities T / (1 + T) and 1 / (1 + T). (c) Discuss your design. What prevents you from further increasing the crossover frequency? How large is the loop gain at 120Hz? Can you obtain more loop gain at 120Hz? + – L C R + v – vg fs = 200kHz 220µF 5Ω50µH –+ compensator vref Hvpulse-width modulator vc transistor gate driver δ Gc(s) H(s) ve VM = 3V 5V Fig. 9.46.