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Lecture 4 in EECS40, Fall 2003: Circuit Elements and Kirchhoff's Laws, Slides of Microelectronic Circuits

A series of slides from a university lecture in the electrical engineering and computer sciences (eecs) department at the university of california, berkeley. The lecture, taught by professor king in the fall 2003 semester, covers the topics of circuit element i-v characteristics, construction of a circuit model, and kirchhoff's laws. Students are encouraged to finish chapter 2 of their reading material and are given instructions for turning in homework assignments.

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2011/2012

Uploaded on 02/27/2012

elmut
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Download Lecture 4 in EECS40, Fall 2003: Circuit Elements and Kirchhoff's Laws and more Slides Microelectronic Circuits in PDF only on Docsity! 1 Lecture 4, Slide 1EECS40, Fall 2003 Prof. King Announcements • Visit the class website to see updated TA section assignments http://www-inst.eecs.berkeley.edu/~ee40 • Lab section 13 (Mondays 6-9PM) is cancelled • Prof. King’s Office Hour tomorrow (Thu. 9/4) will be held from 8:30AM-9:30AM • HW assignments will NOT be accepted in class. Turn in your assignments BEFORE class on Friday in 240 Cory. Lecture 4, Slide 2EECS40, Fall 2003 Prof. King Lecture #4 OUTLINE • Circuit element I-V characteristics • Construction of a circuit model • Kirchhoff’s laws – a closer look Reading (Finish Chapter 2) 2 Lecture 4, Slide 3EECS40, Fall 2003 Prof. King Current vs. Voltage (I-V) Characteristic • Voltage sources, current sources, and resistors can be described by plotting the current (i) as a function of the voltage (v) • Later, we will see that the I-V characteristic of any circuit consisting only of sources and resistors is a straight line. + v _ i Lecture 4, Slide 4EECS40, Fall 2003 Prof. King I-V Characteristic of Ideal Voltage Source 1. Plot the I-V characteristic for vs > 0. For what values of i does the source absorb power? For what values of i does the source release power? 2. Repeat (1) for vs < 0. 3. What is the I-V characteristic for an ideal wire? +_ vs i i + v _ v 5 Lecture 4, Slide 9EECS40, Fall 2003 Prof. King Terminology: Nodes and Branches Node: A point where two or more circuit elements are connected – entire wire Branch: A path that connects two nodes Lecture 4, Slide 10EECS40, Fall 2003 Prof. King Notation: Node and Branch Voltages • Use one node as the reference (the “common” or “ground” node) – label it with a symbol • The voltage drop from node x to the reference node is called the node voltage vx. • The voltage across a circuit element is defined as the difference between the node voltages at its terminals Example: +_ vs + va _ + vb _ a b c R1 R2 – v1 + 6 Lecture 4, Slide 11EECS40, Fall 2003 Prof. King • Use reference directions to determine whether currents are “entering” or “leaving” the node – with no concern about actual current directions Using Kirchhoff’s Current Law (KCL) i1 i4 i3 i2 Consider a node connecting several branches: Lecture 4, Slide 12EECS40, Fall 2003 Prof. King Formulations of Kirchhoff’s Current Law Formulation 1: Sum of currents entering node = sum of currents leaving node Formulation 2: Algebraic sum of currents entering node = 0 • Currents leaving are included with a minus sign. Formulation 3: Algebraic sum of currents leaving node = 0 • Currents entering are included with a minus sign. (Charge stored in node is zero.) 7 Lecture 4, Slide 13EECS40, Fall 2003 Prof. King A Major Implication of KCL • KCL tells us that all of the elements in a single branch carry the same current. • We say these elements are connected in series. Current entering node = Current leaving node i1 = i2 Lecture 4, Slide 14EECS40, Fall 2003 Prof. King KCL Example 5 mA 15 mA i -10 mA 3 formulations of KCL: 1. 2. 3. Currents entering the node: Currents leaving the node: 10 Lecture 4, Slide 19EECS40, Fall 2003 Prof. King A Major Implication of KVL • KVL tells us that any set of elements which are connected at both ends carry the same voltage. • We say these elements are connected in parallel. Applying KVL in the clockwise direction, starting at the top: vb – va = 0 vb = va + va _ + vb _ Lecture 4, Slide 20EECS40, Fall 2003 Prof. King Path 1: Path 2: Path 3: vcva + − + − 3 21 + − vb v3v2 + − + - Three closed paths: a b c KVL Example 11 Lecture 4, Slide 21EECS40, Fall 2003 Prof. King • No time-varying magnetic flux through the loop Otherwise, there would be an induced voltage (Faraday’s Law) Avoid these loops! How do we deal with antennas (EECS 117A)? Include a voltage source as the circuit representation of the induced voltage or “noise”. (Use a lumped model rather than a distributed (wave) model.) • Note: Antennas are designed to “pick up” electromagnetic waves; “regular circuits” often do so undesirably. )t(B v )t(v + − An Underlying Assumption of KVL Lecture 4, Slide 22EECS40, Fall 2003 Prof. King Summary • An ideal voltage source maintains a prescribed voltage regardless of the current in the device. • An ideal current source maintains a prescribed current regardless of the voltage across the device. • A resistor constrains its voltage and current to be proportional to each other: v = iR (Ohm’s law) • Kirchhoff’s current law states that the algebraic sum of all currents at any node in a circuit equals zero. • Kirchhoff’s voltage law states that the algebraic sum of all voltages around any closed path in a circuit equals zero.
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