Datapath and Control - Computer Architecture and Design - Lecture Slides, Slides of Computer Science

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Page 1 1 Ch5 Processor: Datapath and Control • Single cycle processor – Datapath and Control • Multicycle processor – Datapath and Control • Microprogramming – Vertical and Horizontal Microcodes 2 Ch5 Processor Design • Processor design – datapath and control unit design – processor design determines » clock cycle time » clock cycles per instruction • Performance of a machine is determined by – Instruction count – clock cycle time – clock cycles per instruction 3 Ch5 Review: THE Performance Equation • Our basic performance equation is then CPU time = Instruction_count x CPI x clock_cycle Instruction_count x CPI clock_rate CPU time = ----------------------------------------------- or • These equations separate the three key factors that affect performance – Can measure the CPU execution time by running the program – The clock rate is usually given in the documentation – Can measure instruction count by using profilers/simulators without knowing all of the implementation details – CPI varies by instruction type and ISA implementation for which we must know the implementation details 4 Ch5 How to Design a Processor: step-by-step 1. Analyze instruction set => datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers possibly more datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Docsity.com Page 2 5 Ch5 Single Cycle Processor • Single cycle processor – Pros: one clock cycle per instruction – Cons: too long cycle time, too low clocking frequency • Design a processor – analyze instruction set (the meaning of each instruction is given by the register transfers) – timing of each instruction – datapath support each register transfer – select datapath components and establish clocking methodology – analyze implementation of each instruction to determine setting of control points that affect register transfer – assemble control logic and datapath components 6 Ch5 Clocking Methodology • Edge-triggered clock • setup time • hold time • all storage elements clocked by the same clock • combinational logic block: – inputs are updated at each clock tick – all outputs must be stable before the next clock tick 7 Ch5 Clocked Logic Timing 8 Ch5 Timing Analysis, Logic Delay Worst case CL delay limits T. What is the smallest T that produces correct operation? Docsity.com Page 5 17 Ch5 Combinational Logic Elements • Adder • MUX (multi-plexor) • ALU 32 32 A B 32 Sum Carry 32 32 A B 32 Result OP 32A B 32 Y32 Select A dder M U X A L U CarryIn (to add values) (to chose between values) (to do add, subtract, or) 18 Ch5 Storage Element: Register (Basic Building Block) • Register – Similar to the D Flip Flop except » N-bit input and output » Write Enable input – Write Enable: » negated (0): Data Out will not change » asserted (1): Data Out will become Data In Clk Data In Write Enable N N Data Out 19 Ch5 Sequential Logic Elements • Registers: n-bit input and output, D F/F, write enable • rs, rt, rd : register specifiers registers read register1 read register2 write register write data read data1 read data2 20 Ch5 Fetching Instructions • Fetching instructions involves – reading the instruction from the Instruction Memory – updating the PC to hold the address of the next instruction Read Address Instruction Instruction Memory Add PC 4 – PC is updated every cycle, so it does not need an explicit write control signal – Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal Docsity.com Page 6 21 Ch5 Decoding Instructions • Decoding instructions involves – sending the fetched instruction’s opcode and function field bits to the control unit Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Control Unit – reading two values from the Register File » Register File addresses are contained in the instruction 22 Ch5 Executing R Format Operations • R format operations (add, sub, slt, and, or) – perform the (op and funct) operation on values in rs and rt – store the result back into the Register File (into location rd) Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite R-type: 31 25 20 15 5 0 op rs rt rd functshamt 10 – The Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register File 23 Ch5 Executing Load and Store Operations • Load and store operations involves – compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instruction – store value (read from the Register File during decode) written to the Data Memory – load value, read from the Data Memory, written to the Register File Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead 16 32 24 Ch5 Executing Branch Operations • Branch operations involves – compare the operands read from the Register File during decode for equality (zero ALU output) – compute the branch target address by adding the updated PC to the 16-bit signed-extended offset field in the instr Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero ALU control Sign Extend16 32 Shift left 2 Add 4 Add PC Branch target address (to branch control logic) Docsity.com Page 7 25 Ch5 Executing Jump Operations • Jump operation involves – replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Instruction Memory Add PC 4 Shift left 2 Jump address 26 4 28 26 Ch5 Creating a Single Datapath from the Parts • Assemble the datapath segments and add control lines and multiplexors as needed • Single cycle design – fetch, decode and execute each instructions in one clock cycle – no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) – multiplexors needed at the input of shared elements with control lines to do the selection – write signals to control writing to the Register File and Data Memory • Cycle time is determined by length of the longest path 27 Ch5 Fetch, R, and Memory Access Portions MemtoReg Read Address Instruction Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend16 32 ALUSrc 28 Ch5 Adding the Control • Selecting the operations to perform (ALU, Register File and Memory read/write) • Controlling the flow of data (multiplexor inputs) I-Type: op rs rt address offset 31 25 20 15 0 R-type: 31 25 20 15 5 0 op rs rt rd functshamt 10 • Observations – op field always in bits 31-26 – addr of registers to be read are always specified by the rs field (bits 25-21) and rt field (bits 20-16); for lw and sw rs is the base register – addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions – offset for beq, lw, and sw always in bits 15-0 J-type: 31 25 0 op target address Docsity.com Page 10 37 Ch5 38 Ch5 ALU Control Implementation 39 Ch5 On page 301, ALU control lines = Operation ALU control lines Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set on less than 1100 NOR 40 Ch5 0111set on less than 101010set on less than 10R type 0001or100101OR10R type 0000and100100AND10R type 0110subtract10010subtract10R type 0010add100000add10R type 0110subtractxxxxxxbranch equal 01Branch equal 0010addxxxxxxstore word00SW 0010addxxxxxxload word00LW ALU control input, i.e., Operation Desired ALU action Funct field Instruction operation ALUOPinstruction opcode Docsity.com Page 11 41 Ch5 Setting of the control signals 101000x0xbeq 000100x1xsw 000011110lw 010001001R type ALU Op0 ALU Op1 BranchMem Write Mem Read Reg Write Memto Reg ALUSrcRegDstInstru- ction 42 Ch5 43 Ch5 Control Unit PLA Implementation 44 Ch5 Single Cycle Disadvantages & Advantages • Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction – especially problematic for more complex instructions like floating point multiply • May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but • Is simple and easy to understand Clk lw sw Waste Cycle 1 Cycle 2 Docsity.com Page 12 45 Ch5 Multicycle Datapath Approach • Let an instruction take more than 1 clock cycle to complete – Break up instructions into steps where each step takes a cycle while trying to » balance the amount of work to be done in each step » restrict each cycle to use only one major functional unit – Not every instruction takes the same number of clock cycles • In addition to faster clock rates, multicycle allows functional units that can be used more than once per instruction as long as they are used on different clock cycles, as a result – only need one memory – but only one memory access per cycle – need only one ALU/adder – but only one ALU operation per cycle 46 Ch5 Multicycle Datapath Approach • Let an instruction take more than 1 clock cycle to complete – Break up instructions into steps where each step takes a cycle while trying to » balance the amount of work to be done in each step » restrict each cycle to use only one major functional unit – Not every instruction takes the same number of clock cycles • In addition to faster clock rates, multicycle allows functional units that can be used more than once per instruction as long as they are used on different clock cycles, as a result – only need one memory – but only one memory access per cycle – need only one ALU/adder – but only one ALU operation per cycle 47 Ch5 • At the end of a cycle – Store values needed in a later cycle by the current instruction in an internal register (not visible to the programmer). All (except IR) hold data only between a pair of adjacent clock cycles (no write control signal needed) IR – Instruction Register MDR – Memory Data Register A, B – regfile read data registers ALUout – ALU output register Multicycle Datapath Approach, con’t Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR M D R A B A LU ou t – Data used by subsequent instructions are stored in programmer visible registers (i.e., register file, PC, or memory) 48 Ch5 The Multicycle Datapath with Control Signals Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR M D R A B AL U ou t Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource 1 1 1 1 1 1 0 0 0 0 0 0 2 2 3 4 Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28 Docsity.com Page 15 57 Ch5 58 Ch5 59 Ch5 60 Ch5 Docsity.com Page 16 61 Ch5 62 Ch5 63 Ch5 64 Ch5 Docsity.com