Design Customized Plug in Power Supply - Power Electronics I | ECE 562, Lab Reports of Electrical and Electronics Engineering

Download Design Customized Plug in Power Supply - Power Electronics I | ECE 562 and more Lab Reports Electrical and Electronics Engineering in PDF only on Docsity! LAB1 —- WEBENCH SIMULATION EE562: POWER ELECTRONICS COLORADO STATE UNIVERSITY Simulation Using WEBENCH - 1 - PURPOSE: The purpose of this lab is to explore National Semiconductors WEBENCH, which is an online design and prototyping tool. WEBENCH provides a plug-in power supply design which is customized to particular specifications. This is an on-line environment which saves time in the design process. Design, optimize, generate a prototype, and download test vectors—all online. This can all be done for free, anywhere, anytime. This lab will introduce the following aspects of WEBENCH. • Design a customized plug-in power supply • Vary CSS • Vary COUT • Vary Inductors • Discuss tradeoffs between components Design a customized plug-in power supply Through four steps, WEBENCH enables its users to quickly design a power supply customized to their specifications. 1. Choose a part based on your specifications 2. Create a design including passive components and important calculated operating values 3. Analyze a design using the WEBENCH electrical simulation 4. Build it and take your virtual design to the real world The focus will be to create a power supply design. WEBENCH can be accessed through the menu bar on the National web site homepage (be sure to select power). The first step is to enter the power supply design requirements in the design tool displayed. For this design we will select the following: Simulation Using WEBENCH - 4 - The previous plot shows the startup simulation with CSS = 1 nF. It can be seen that the time to reach 5 volts is now 0.5 milliseconds. From this screen, open the Add Waveform window and select the previous Startup simulation in order to view both plots side by side. The green line shows VOUT for CSS = 1 nF and the red line shows VOUT for CSS = 4.7 nF. Simulation Using WEBENCH - 5 - It can be seen that the time to reach 5 volts is decreased from 1.8 milliseconds to 0.5 milliseconds by reducing the value of CSS. Load Transient Next, the Load transient will be investigated. In the “Select Simulation Type” choose Load Transient and click the Start New Simulation button. Here both the load transient pulse in blue and the corresponding VOUT waveform in red can be seen. There is an overshoot of about 100 mV when the load current is falling and an undershoot of a slightly smaller amount when the load current is rising. Zoom in on a section of the waveform by clicking and dragging with the mouse to get a closer look at the peak-to-peak change in voltage. Simulation Using WEBENCH - 6 - In the zoomed-in view, the peak-to-peak output ripple at full load can be estimated, to be less than 4 mV. Bode Plot The focus will now be on the Bode plot function. Bode plot is an important tool to examine the stability of a design. In the “Select Simulation Type” choose Bode Plot and click the Start New Simulation button. -The Bode Plot shows the phase and gain on the same graph plotted vs. frequency. -The phase margin should be at least 25 degrees but preferably 45 degrees. -The phase margin is the difference between the phase and -180 degrees measured at the point where the gain = 0 dB (crossover frequency) -The phase is not of concern when the gain drops below zero. -If the phase approaches -180 at frequencies below crossover and it comes back up, that is conditional stability which is acceptable as long as the phase is good at the crossover frequency. Simulation Using WEBENCH - 9 - Compare the simulations side by side. This is a WEBENCH Bode Plot showing different output capacitor ESRs. Both simulations show a dip in the phase at about 3kHz. This is called conditional stability. From the plot the conditional stability issue can be improved by lowering the ESR of the output capacitor. This also increases the crossover frequency and bandwidth. Effect of Cout on load transient The effect of raising the COUT ESR on the output voltage during a load transient test will now be examined. Simulation Using WEBENCH - 10 - This simulation shows the initial Load Transient simulation where COUT ESR = 4 milliohms. This simulation shows the initial Load Transient simulation where COUT ESR = 40 milliohms. Simulation Using WEBENCH - 11 - The green waveform represents VOUT with the initial capacitor of lower ESR. The overshoot as the current ramps down has decreased slightly and the undershoot has increased slightly. The other effect of changing the output capacitor is that the voltage ripple will change. The ripple has increased with increasing ESR on COUT from approximately 3 mV to 15 mV peak to peak. Vary Inductors Next, we will investigate the effect of inductance on our design. Again, run two bode plot simulations: one using a 33 µH inductor and another using a 47 µH inductor. Simulation Using WEBENCH - 14 - Load transient simulation for L1 = 47 µH The load transient response is plotted for the two inductances. The green line corresponds to the 47 µH inductor while the red line represents the 33 µH inductor. For this design, the 33uH value results in less excursion during the load transitions. Simulation Using WEBENCH - 15 - Ripple effects Effect of inductance on inductor/switch ripple current Now, view the peak current across the inductor. Run a steady-state simulation and select the Inductor waveform for each inductance value. Inductor current during steady state for L=33µh Simulation Using WEBENCH - 16 - Inductor current during steady state for L = 47 µH. Notice that the peak-to-peak inductor current, ILPP, is reduced from .375A to .25A by increasing the inductor from 33µH to 47µH. The peak inductor current was also reduced from about 3.2A to about 3.125A. This follows since: ILPEAK = ILAVERAGE + .5ILpp where ILAVERAGE = IOUT (assume L is ideal). Since VOUT ripple = inductor ripple current * COUT ESR Higher inductance means a lower VOUT ripple. The trade off is a larger footprint and a higher cost. Simulation Using WEBENCH - 19 - Use load transient simulations to see the effects of changing COUT has on the voltage output response. How is the overshoot and undershoot effected? Show the various simulations of each COUT on the same plot. How is the voltage ripple affected? Investigate the effect of inductance on your design. L1_1: Inductance _____________________ Manufacturer _____________________ Range in cost _____________________ ILPEAK ________________________________ L1_2: Inductance _____________________ Manufacturer _____________________ Cost _____________________ ILPEAK ________________________________ Simulation Using WEBENCH - 20 - Show bode plots for each inductor. L1_1: 33µH L1_2: 47µH How is the phase effected? Comment on the effects of the VOUT load transient during the rise and fall times of a current pulse. How is the VOUT ripple affected for various inductances? Simulation Using WEBENCH - 21 - Use the steady state simulation and display the current across L1 in steady state. How is the peak current across the inductor changed? _________________________ How is the VOUT ripple affected? _____________________________________ What should be considered when using alternate inductances? _________________ How much does an LM2673-5.0 evaluation board cost? _______________________ How does this price compare to other switching regulators offered by National and competing retailers? _____________________________________________________ WRITTEN REPORT: When writing the report, answer all questions posed throughout this lab. Written Report shall include: • Cover page • Purpose • Answers to questions • All Necessary WEBENCH plots • Conclusion