Design Interface and Verification-I - Lecture Slides | CPSC 489, Study notes of Computer Science

Download Design Interface and Verification-I - Lecture Slides | CPSC 489 and more Study notes Computer Science in PDF only on Docsity! 1 Mahapatra-A&M-Fall’00 1 Design Interface and Verification-I Introduction to a model of interfacing components in a design; and its verification. Mahapatra-A&M-Fall’00 2 Interfacing components • Process is an independent part of a computation done concurrently with other parts. (VHDL, UNIX) • Thread is used in Java. • Component in Codesign: COMPONENT name declaration ,local quantities of components used in computation computation 2 Mahapatra-A&M-Fall’00 3 Telephone switch components ♦ COMPONENT unit , ( physical phone that detects the off-hook, sends id, and disconnects) p:phone_connector ….(* computation*) END unit • COMPONENT connect , (check receiver not busy, free capacity : arbiter) • COMPONENT transfer , (transmits digitized sound from common memory, data transmission constantly in both directions) Mahapatra-A&M-Fall’00 4 Interfacing components • Interface determines the coordination of the components including their data transfer and synchronization. • Codesign demands heterogeneous interface modeling. – Can not favor any one existing technology or signaling discipline alone. A B component component Interface 5 Mahapatra-A&M-Fall’00 9 Verification • Verification is important for non-trivial design projects. • Ideally, all exhaustive check is required but seldomely possible in practice. • Formal methods are more recent. – Formality is a possibility but should not be mandatory. • Three kinds of formal methods are used at different stages of design process: – Interface verification – design verification – Implementation verification Mahapatra-A&M-Fall’00 10 Interface verification What is interface verification? • Separate design to distinct components is common • components interact through interface using coordination mechanism following the protocols – Designers might treat details on signaling differently across various components. Leads to inconsistency. ⇒ Interface verification checks this inconsistencies. 6 Mahapatra-A&M-Fall’00 11 Design verification What is design verification? • Consists of verifying selected key requirements of incomplete models. • Example: Arbiter – At most one device has access to common resources (mutual exclusion). Once the interface to bus has been designed, it is possible to verify that it does not violate the mutual exclusion property, even if other components of the design are still missing. Mahapatra-A&M-Fall’00 12 Implementation verification • To construct efficient product, it is necessary to refine initial design into concrete realization - typically includes a number of restrictions. (e.g. restrict integer values to a certain range so that you use fixed number of bits) • Clearly, it requires that the concrete realization has been done and hence implementation verification is relevant rather late in design process. • Now available in commercial design system. 7 Mahapatra-A&M-Fall’00 13 Simplified Arbiter as an example COMPONENT arbiter(reql, grl, reqr, grr: BOOLEAN) INITIALLY grl = FALSE grr = FALSE << reql ∧ ¬grr → grl:= TRUE>> || << ¬ reql ∧ grl → grl:= FALSE>> || << reqr ∧ ¬grl → grr:= TRUE>> || << ¬ reqr ∧ grr → grr:= FALSE>> END arbiter Would check grr and grl are never both true. This is mutual exclusion, to beasserted, ¬ (grl ∧ grr). Reading assignment: Section 6.5.1 of Text Arbiter Client Left Client Right reql grl grr reqr Mahapatra-A&M-Fall’00 14 Interface Verification • How is it possible to verify that different components have a consistent view of their interface? – Allow them to have different views as long as these are not in conflict. • EX: packet in communication protocol. – An uninterrupted collection of bits to be transmitted vs. structured packet with different fields indicating addresses, control and checksum. In codesign computational model, interface of component consists of “set of state variable” and a “protocol”.