VLSI Design & FPGA Architecture: Parasitic Elements, Regularity, Locality, Package Bonding, Study notes of Electrical and Electronics Engineering

Download VLSI Design & FPGA Architecture: Parasitic Elements, Regularity, Locality, Package Bonding and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! ESE 570 VLSI DESIGN METHODOLOGIES Kenneth R. Laker, University of Pennsylvania, updated 29Jan08  Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 2 Extract Parasitic Elements Three Domain View of VLSI Design Flow at One Level 1. Design Rule Check (DRC) 2. Layout Versus Schematic (LVS) Check SPICE (Spectre) Verilog/Cadence Cadence (Virtuoso) Verilog MODULARITY ADDS TO HIERARCHY AND REGULARITY THE QUALITIES OF WELL DEFINED FUNCTIONS AND INTERFACES -> Unambiguous functions -> Well defined behavioral, structural, and physical interfaces -> Enables modules to be individually designed and evaluated. Kenneth R. Laker, University of Pennsylvania, updated 26Mar09  Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 add4 add add addadd sum car ry sum ca rr y sum c ar ry sum c arr y nand nor nand nor nand nor nand nor Hierarchical & Modular 4-bit Adder +a b c co s inv inv inv inv c a b sum c a b carry s co + + + + a[3:0] b[3:0] s[3:0] co3 c0 6 + + + + a[3:0] b[3:0] s[3:0] co3 c0 a[0] a[1] a[2] a[3] b[0] b[1] b[2] b[3] s[3] s[2] s[1] s[1]add[0] add[1] add[2] add[3] c0 co3 (100,100) (100,200) (100,300) (100,400) (0,100)(0,0) Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 b[i] a[i] s[i] c[i] co[i] add[i] (100,100) (100,50) (100,0) (50,0) (50,100) (0,0) (0,25) (0,75) add4 Layout add Cell 7 add4 Hierarchical & Modular Layout Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 10 LOCALITY (PHYSICAL) TIME LOCALITY: modules are synchronized by common clock. -> Critical timing paths are kept within module boundaries or within near neighbor boundaries. -> Place modules to minimize large or “global” inter-module signal routes. -> Care take to realize robust clock generation and distribution. -> Signal routes between modules with large physical separation need sufficient time to traverse route. -> Replicate modules, if necessary, to alleviate delay issues caused by long inter- module signal routes. Performance Increasing, Die Are Decreasing, Power Dissipation Decreasing (for a given application) Time-to-Market and Design Investment Increasing (for a given application) Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 11 STANDARD-CELLS (POLYCELL) BASED DESIGN 2 -> Predominant full-custom design style. -> Standardization is achieved at the logic or function level. -> Specific designs for each gate can developed and stored in a software database or cell library. + Behavioral, Structural, and Physical Domain descriptions per cell -> Layout is usually automatically placed and routed using CAD software. Typical Standard Cell Library contents: -> SSI logic: e.g. nand, nor, xor, inverters, buffers, latches, registers + Each gate can have multiple implementations to provide proper drive for different fan-outs, e.g. standard size, 2x, 4x -> MSI logic: e.g. decoders, encoders, adders, comparators -> Datapath: e.g. ALUs, adders, register files, shifters -> Memories: e.g. RAM, ROM -> System level blocks: e.g. multipliers, microcontrollers Kenneth R. Laker, University of Pennsylvania, updated 26Mar09  Basic FPGA Architecture Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 15 (Configurable Logic Blocks - CLBs) Segmented Routing Tracks I/O Modules Logic Modules Clock Buffer Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 http://www.latticesemi.com/products/fpga/ecp2/optimizedfpgaarchitecture.cfm 16 State-of-the-Art FPGA Architecture Programmable Function Unit (PFU) – perform logic, arithmetic, Distributed RAM & ROM functions. Flexible Sys I/O Buffers – support LVCMOS, LVDS, etc. Sys Clock – PLLs & DLLs for clock management. Configuration Port – supports SPI, serial and parallel configuration. Sys DSP Blocks – implement multipliers, adders, subtractors, accumulators. Embedded 3.125 Gbps SERDES – support PCI express, Ethernet. DESIGN QUALITY -> ACHIEVE SPECIFICATIONS (Static & Dynamic) ->DIE SIZE ->POWER DISSIPATION -> TESTABILITY -> YIELD AND MANUFACTURABILITY -> RELIABILITY Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 17  Package Bonding Techniques Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 20 Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 21 Flip-Chip Bonding Package Bonding Techniques Kenneth R. Laker, University of Pennsylvania, updated 26Mar09 22Summary of Package Types