Download CMOS Operational Transconductance Amplifier Design Project at UC Santa Barbara and more Study Guides, Projects, Research Geography in PDF only on Docsity! University of California, Santa Barbara Department of Electrical & Computer Engineering CMOS Analog VLSI I ECE 194A/594A Professor Theogarajan Design Project 2, Due December 8, 2008 As transistor channel lengths start to decrease, it becomes harder to design analog circuits in theses processes. Nevertheless, designing high performance analog circuits is necessary for high performance A/D, D/A and filters. This design project will highlight some of the obstacles that you might face as an analog designer. You can work in teams of 2 or individually if prefer. You are expected to turn in a hard-copy of a power-point presentation of your design which you will then present in class. The duration of the presentation is 20 minutes with 5-10 minutes for questions. You are advised to start early!!! GOOD LUCK! For NMOS Devices Strong-Inversion: Linear Region: Ids = µnCoxW L [( Vgs − Vtn − Vds2 ) Vds ] Saturation: Ids = µnCoxW 2L [ (Vgs − Vtn)2 (1 + λVds) ] Weak Inversion(Subthreshold): Ids = I0nW exp qVgs nkT exp −q(n−1)Vsb nkT ( 1− exp −qVds kT ) (1 + λVds) For PMOS Devices: Strong-Inversion: Linear Region: Isd = µpCoxW L [( Vsg − |Vtp| − Vsd2 ) Vsd ] Saturation: Isd = µpCoxW 2L [ (Vsg − |Vtp|)2 (1 + λVsd) ] Weak Inversion(Subthreshold): Isd = I0pW exp qVsg nkT exp −q(n−1)Vbs nkT ( 1− exp −qVsd kT ) (1 + λVds) For the 0.18µm TSMC process you can use the following in your hand calculations. Note that this is valid only for the minimum channel length of 0.18µm. The channel length mod- ulation parameter can be found by simulation, you may (at your own risk) use a value of 0.1 for a channel length of 0.18µm in strong inversion. In weak inversion this will degrade and you can use a value of around 0.4 Vtn = |Vtp| = 0.5V µnCox 2 = 175µA V 2 µpCox 2 = 35µA V 2 I0n = 20 pA µm I0p = 10 pA µm For PMOS & NMOS n = 1.2 ECE 194A/594A Design Project 2 Due December 8, 2008 1. The goal of this design project is to design a fully differential high-gain , high-bandwidth CMOS operational transconductance amplifier with a large dynamic range The following constraints must be met. 1. The bias current for your amplifier must be derived from a bias generator. Prefer- ably you will use the design from you design project 1. 2. The open-loop gain of your amplifier must be ≥ 100dB 3. The unity gain frequency of your design must be ≥ 50MHz for a 1pF load to ground on each output. 4. An input common-mode range of ≥ ±200mV at a supply voltage of 1V 5. The circuit must operate reliably (i.e meet all specs) in a supply range of 1V ≤ Vdd ≤ 1.8V . 6. Power dissipation ≤ 250µW with a 1.8V power supply including the bias network. 7. A CMFB Circuit is expected for this fully differential design 8. An output swing of 1.5V for a 1.8V supply 9. Worst Case Systematic offset of 1mV 10. Settling time of ≤ 120ns to settle with 0.1% of the final value 11. A Common mode rejection ratio (CMRR) ≥ 70dB at an input common-mode equal to Vdd 2 12. A phase-margin of ≥ 50◦, additionally you may not use compensation capacitors greater than 5pF. 13. Power-Supply Rejection Ration (PSRR+,PSSR-) ≥ 70dB at 100kHz. The PSRR+ refers to the a voltage applied on VDD and PSSR- to an ac votage applied between the negative rail and gnd. For this you will have to tie all the NMOS nodes normally at GND to a pin. 14. A dynamic range ≥ 83dB at a supply voltage of 1.8V. Dynamic range is given by DR = Voutput swing Input Referred Noise For a 1.8V supply with an output swing of 1.5V this translates to ∼= 100µV of input referred noise of in-band noise given by (√ V 2noise Hz × Unity gain bandwidth ) when the amplifier is in unity gain configuration driving a 1pF load. 15. The circuit must be minimally sensitive ( i.e. meet all specifications) to process variation. Some additional things you should consider 1. You will be graded on the overall size of your circuit 2. Using widths > 100µm or lengths > 1.8µm will result in points being deducted.
