Computer Architecture and Design Project Challenges: Memory Module and FPGA Limitations - , Study Guides, Projects, Research of Computer Architecture and Organization

Download Computer Architecture and Design Project Challenges: Memory Module and FPGA Limitations - and more Study Guides, Projects, Research Computer Architecture and Organization in PDF only on Docsity! Ryan McPherson Nesha Hyatt ELEC 5200/6200 Computer Architecture and Design Design Project Part 5 The Design project as a whole went well for us. We were able to fully implement a multicycle design both in Modelsim and on the FPGA. We are confident that any we could run almost any program on our processor. However, there were a number of issues, specifically with the implementation of the FPGA that should be mentioned. The first major issue is that the memory module for the FPGA is clocked, meaning that it can only be accessed on a rising clock edge. This immediately creates major problems for anyone who has a single cycle design—hoping to read and write on different edges. In the end this was the main reason for our design change after part 4: our original singlecycle design was scrapped for a multicycle one a week before the demo of the FPGA. Fortunately we were still able to finish in time, but clearly this information about the memory module needs to be presented early on to the students in the future. Another caveat is that should be mentioned is the need to show that the demo was not “rigged.” Of course this is important in any demonstration and we should have realized this sooner. While the given “test.c” file does a good job of forcing the processor to complete each of the required functions, it is rigid and changing values requires recompiling the binary. The simplest thing to do would be to make sure the ISA has an operand that would take a user input at the start of the program. Unfortunately, by the time we realized this we were spending most of our time debugging the program on the FPGA. Given more time, we would have made the necessary hardware changes. Also, we would have liked to include things like hazard detection, and perhaps changed the system to a pipeline Overall, the project did an excellent job of giving the students experience designing a processor from the ground up. While there were some issues, they can be easily resolved by simply learning a bit more information about the FPGA at the start.