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Design Review - No Doze EEG Sleep Detector - Project I | ECE 445, Study Guides, Projects, Research of Electrical and Electronics Engineering

Material Type: Project; Class: Senior Design Project Lab; Subject: Electrical and Computer Engr; University: University of Illinois - Urbana-Champaign; Term: Fall 2006;

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Download Design Review - No Doze EEG Sleep Detector - Project I | ECE 445 and more Study Guides, Projects, Research Electrical and Electronics Engineering in PDF only on Docsity! Design Review: No Doze EEG Sleep Detector Developers: Benjamin Schneider David Mahr Kuang Tan ECE 445 Senior Design Laboratory Professor Makela T.A. Hyesun Park September 25, 2006 Introduction: Purpose: We intend to develop a life saving device that will alert drivers that are drowsy or have fallen asleep. Fatigue exists as the direct cause of approximately hundred thousand crashes in the United States each year. Additionally, drowsiness is a major contributor to driver inattention: the cause of one million crashes annually, or one-sixth of all crashes. We chose this project because a device that could prevent the many injuries, fatalities, and monetary losses associated with these automobile accidents would be very beneficial to the welfare of our society. Objectives: An appreciable difference exists between brainwaves of a person that is awake and a person that is on the verge of sleep. As a person transitions from alertness to sleep, the alpha rhythms of his/her brainwaves decrease in frequency, diminish in amplitude, and become more irregular in frequency. These brainwave changes can be sensed using an electroencephalogram (EEG). Our goal is to develop a device that will recognize the shift from wakefulness to sleep, via proper signal processing of the EEG output, and then relay that information wirelessly to an alarm system. The alarm system will display the awareness level of the user and alert the user that he/she is near to or has falling asleep. Our device, therefore, will consist mainly of an EEG, signal processing equipment, wireless linking system, and an alarm system. Benefits:  Driving Related Applications o Elimination of fatigue/drowsiness related car accidents  1,500 less highway fatalities per year  71,000 less motor-vehicle related injuries per year  $12.5 billion saved per year o Provide late night drivers with a sense of safety  Medical/Everyday Applications o Keep hospital patients with concussions awake o Avoid nodding off at work o Stay awake in class Product Features:  Housing of EEG and signal processing components in a headset  Lightweight and comfortable  Wireless relay from headset to alarm system  Alarm that increases in volume until person is awake  LED strip showing the user’s level of awareness  Log of instances of sleep or near sleep (severe drowsiness)  Earpiece, vibration, and music alarm options Figure 6 – Awareness LED Circuit 4 3 2 1 1 2 1 1 1 0 9 87 6 5 7 4A CT 11 0 74 1 4 1 3 2 3 4 1 3 1 4 1 1 1 1 2 6 7 1 0 1 6 7 4A C1 10 0 8 5 9 1 5 2 8 1 3 4 3 1 1 4 6 1 2 1 1 1 6 1 07 5 74 AC 11 03 2 8 1 5 9 1 3 2 3 4 6 1 4 1 1 6 1 1 1 2 7 1 0 8 74 AC 11 00 0 5 9 1 5 V C C _ B A R V C C _ B A R V C C _ B A R V C C _ B A R T o R S S I G i n p u t o n L E D R i n p u t o n L E D C o n n e c t e d t o s w i t c h i n p u t f r o m r e c e i v e r d a t a p i n Figure 7 – Polarity Protection Polarity protection circuit is used to power devices that requires +5V to regulate the supply of power. Figure 8 – Voltage Protection for PIC The voltage protection circuit is placed in series between output of the EEG circuit and the PIC A/D. This is used in order to protect the PIC from a dangerously high voltage that could be amplified by the EEG circuit. Schematic Descriptions: EEG Module: The input to the EEG circuits consists of three electrodes. These electrodes are Ag/AgCl electrodes to provide a proper impedance matched conduction surface to the skin. Electrodes are placed on the back of the head above the occipital lobe, on the forehead above the frontal lobe and the neck to serve as ground. The two electrodes on the head serve as the main inputs to the EEG circuit. The leads from the electrodes are connected in series with 4.7K ohm resistors followed by two AC Fuse (eg. 1A) 1N5339 (eg. 5.6V) Parts shop: 1N4734 + D.U.T. – (+ ) (– ) Zener diode + D.U.T. – 1N4001 couplings. This serves as two passive filters, one high pass and the other low pass with cutoff frequencies: RC f 2 1  The high pass filter has a cutoff of .34 Hz and the low pass filter has a cutoff of 48.23 Hz. The purposes of these filters are to reduce DC offset as well as noise related to specifically to power lines. This is acceptable because the frequencies we are concerned with are from 4 Hz to 30 Hz. Next, the outputs of the filters are connected to an op-amp with unity gain. This is known as a buffer circuit. The main purpose of the buffer circuit is to reduce drift current which could affect the output of the EEG. These outputs are then connected to an instrumentation amplifier. In the schematics we show how an instrumentation amplifier is constructed out of op-amps and resistors. We chose to use an instrumentation amplifier instead of building one ourselves from op-amps because they are manufactured with the purpose for EKG/EEG use. Building one ourselves would cause a much poorer instrumentation amplifier because the resistance of resistors vary by a small percentage as to what they are labeled as and can cause problems with noise. We chose to use the AD8221 manufactured by Analog Devices. The AD8221 is a high performance instrumentation amplifier, with a high CMRR, and a differential gain of up to 1000. Because the signal generated at the electrodes is on the order of 100uV, we plan to use two instrumentation amplifiers in series to produce a gain of 10,000. The equation for gain in the instrumentation amplifier is: Rg= 49.5kΩ G - 1 In both amplifiers, we desire a gain of 100. Therefore we simply connect a 495 resistance across the Rg pins (pins 2 and 3). These are connected in series resulting in a gain of 10,000. (G1 x G2 = 100x100 = 10,000) The output of the instrumentation amplifier is then sent to a 4th order butterworth low pass filter. This is an active filter built using op-amps and will have much better defined cut-offs than the two passive filters before the amplifier. The cutoff of the 4th order filter is set to 40 Hz. This is used to further reduce the noise one last time before the signal is sent to the PIC for signal processing. Signal Processing Module: A PIC16F877A exists as the main component of the signal processing portion of the device. The output of the EEG circuit exists as the only input signal to the PIC. This signal is filtered and amplified by the EEG circuit to limit the frequency content to frequencies less than 40 Hz and the voltage to between 0 and +5V. This analog input signal is converted to a digital signal via the PIC’s internal ADC. The sampling rate of Table 1: Pin designation for part TXM-900-HP3-PPS Pin# Name Description Equivalent Circuit 1 GND Analog Ground 2 ANT 50 – ohm RF input 3 CS0 Channel select 0 4 CS1 / SS CLOCK Channel Select 1/ Serial Select Clock. Channel select 1 when in parallel channel selection mode, clock input for serial channel selection mode. 5 CS2 / SS DATA Channel select 1/ Serial Select Data. Channel select 2 when in parallel channel selection mode, data input for serial channel selection mode. 6 CTS Clear-To-Send. This line will go high when the transmitter is ready to receive data. 7 PDN Power Down. Pulling this line low will place the receiver into a low- current state. The module will not be able to receive a signal in this state. 8 VCC Supply voltage (2.8V – 13V) 9 MODE Mode Select. GND for parallel channel selection, VCC for serial channel selection 10 DATA Digital / Analog Data input. This line will output the demodulated digital data Table 2: Pin designation for part RXM-900-HP3-PPS PIN # Name Description Equivalent Circuit 1 ANT 50 – ohm RF input 2-8 GND Analog Ground 9 NC No connection 10 CS0 Channel select 0 11 CS1 / SS CLOCK Channel Select 1/ Serial Select Clock. Channel select 1 when in parallel channel selection mode, clock input for serial channel selection mode. 12 CS2 / SS DATA Channel select 1/ Serial Select Data. Channel select 2 when in parallel channel selection mode, data input for serial channel selection mode. 13 PDN Power Down. Pulling this line low will place the receiver into a low- current state. The module will not be able to receive a signal in this state. 14 RSSI Received Signal Strength Indicator. This line will supply an analog voltage that is proportional to the strength of the received signal. 15 MODE Mode Select. GND for parallel channel selection, VCC for serial channel selection 16 VCC Supply voltage (2.8V – 13V) 17 AUDIO Recovered Analog Output (1 Vpp Analog Output) 18 DATA Digital Data Output. This line will output the demodulated digital data. Buzzer Module: The buzzer circuit will receive two inputs from the PIC. These inputs will be used as the select bits on a 4:1 multiplexer. The piezo-buzzer emits the loudest sound at its maximum current level (10mA for 12V). The intensity of the sound emitted decreases with decreasing current. Depending on the value of the select bits, the buzzer will be supplied with either 10 mA, 7.3 mA, 5.8 mA, or 0, as calculated below. Vmax = Imax*Rinternal 12V = (10mA)*Rinternal Rinternal = 1200Ω) connected to the input/output pins was calculated based Vmax = I3*(Rinternal + 880Ω) connected to the input/output pins was calculated based) 12V = I3*(2080Ω) connected to the input/output pins was calculated based) I3 = 5.8 mA Vmax = I2*(Rinternal + 440Ω) connected to the input/output pins was calculated based) 12V = I2*(1640Ω) connected to the input/output pins was calculated based) I2 = 7.3 mA Vmax = I1*(Rinternal) 0 = I1*(2080Ω) connected to the input/output pins was calculated based) I1 = 0 The current level and therefore the buzzer volume will be selected by the inputs provided by the PIC. This will allow our alarm buzzer to increase in volume over time. Awareness LED Module: Input: RSSI pin, Data pin from receiver, Output: LED illumination. Parts: RGB LED, 74ACT11074 (D-flip-flop), 74AC11008 (AND-Gate), 74AC11032 (OR-Gate), 74AC11000 (NAND-Gate) The LED circuit functions by waiting for a up or down transition (Green, Yellow, Red) from the PIC (data bit via the wireless transmitter). The change in input data for the RGB LED input (B is not used) is determined by the clock pulse (rising edge) for the D-flip flops that keep the previous state of the LEDs. The clock pulse is determined by the RSSI input from the receiver module. RSSI is low when the transmitter is powered down, and high when the transmitter is powered up. At the rising edge, the D flip-flop reads the result from the logic circuit comprising of AND, NAND and OR gates. The following is the logic: Led K-map G’ R’ A G R Current color/Action LED color 1 0 0 1 1 Green/down Yellow 1 0 1 1 0 Green/up Green 0 0 0 1 0 Non-func Blue 0 0 1 1 0 Non-func Blue Buzzer Module:  To test the buzzer module we will provide the module with all the possible inputs (‘00’, ‘01’, ‘10’, or ‘11’). For each input value, we will monitor the current supplied to the buzzer and the intensity of the sound emitted by the buzzer. Awareness LED Module:  The input of the circuit is simulated by using a debounced switch to simulate responses from the PIC (high or low). The outcome of the LED (color) is then verified using the sequence of events from the switch. So, switch will transmit ‘1’ or a ‘0’ and the LED should show proper change of color and that shows the logic circuit works. Logic delay and simulation will be determined by software. Simulations: Differential Amplifier Simulation: Gain= -10000 Input: Sinusoid, Amplitude 100uV, Frequency 8Hz Output: Sinusoid, Amplitude 1 V, Frequency 8Hz Filtered Simulations: Input: Frequency Sweep from 0 to 100 Hz, Amplitude 100uV Cost Analysis: Part Number Manufacturer Description For Status Price Qty Total N/A N/A Ag/AgCl Electrodes EEG Obtained $0.19 3 $0.57 AD8221 AD Instrumentation Amplifier EEG In Transit $1.99 3 $5.97 AD8698 AD Op-Amp EEG In Transit $2.25 3 $6.75
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