Design with Multiplexes - Computer Architecture | CPSC 5155G, Study notes of Computer Architecture and Organization

Download Design with Multiplexes - Computer Architecture | CPSC 5155G and more Study notes Computer Architecture and Organization in PDF only on Docsity! Design with Multiplexers Consider the following design, taken from the 5th edition of my textbook. This is a correct implementation of the Carry–Out of a Full Adder. In terms of Boolean expressions, this is F(X, Y, Z) = (3, 5, 6, 7). We try this with a common circuit emulator, such as Multi-Media Logic, and find that we need to think about more. Page 1 of 13 pages An Eight–to–One MUX in Multi–Media Here is the circuit element selected in the Multi–Media Logic tool. This is an 8–to–1 MUX with inputs labeled 7 through 0, or equivalently X7 through X0. This is expected. The selector (control) lines are as expected; 2 through 0. In my notes, I use M for the output of the Multiplexer. This figure uses the symbol Y (not a problem) and notes that real multiplexers also output the complement. The only issue here is the enable. Note that the MUX is enabled low; this signal must be set to ground in order for the multiplexer to function as advertised. Page 2 of 13 pages Testing the Carry–Out Circuit If the Enable switch is set to 1, the output is always 0. Y’ = 1. Set the Enable switch to 0 and generate the following sequence. Start with S2 = 0, S1 = 0, S0 = 0. 0 0 0 Click S0 to get 0 0 1 Click S1 to get 0 1 1 Click S0 to get 0 1 0 Click S2 to get 1 1 0 Click S0 to get 1 1 1 Click S1 to get 1 0 1 Click S0 to get 1 0 0 Page 5 of 13 pages Design with Decoders We now look at another circuit from my textbook. This shows the implementation of a Full Adder with an active high decoder and two OR gates. The outputs are: F1 the Sum F2 the Carry–Out F1(A, B, C) = (1, 2, 4, 7) = (0, 3, 5, 6) F2(A, B, C) = (3, 5, 6, 7) = (0, 1, 2, 4) PROBLEM: Almost all commercial decoders are active low. Page 6 of 13 pages Active Low Decoders First, let’s use 3–to–8 decoders to describe the difference between active high and active low. In the active–high decoder, the active output is set to +5 volts (logic 1), while the other outputs are set to 0 volts (logic 0). In the active–low decoder, the active output is set to 0 volts (logic 0), while the other outputs are set to +5 volts (logic 1). Page 7 of 13 pages Back To Active High: A Look At F2 Seeking a gate that outputs 1 if at least one of its inputs is 1, we are led to the OR gate. Page 10 of 13 pages Active Low: F2(X, Y, Z) = (0, 1, 2, 4) F2 is 1 if and only if none of the outputs Y0, Y1, Y2, or Y4 are selected. Specifically, each of those outputs must be a logic 1. This leads to an AND gate implementation. Page 11 of 13 pages Where are the Decoders? One will note that the Multi–Media Logic tool does not provide a decoder circuit. Fortunately, a 1–to–2N demultiplexer can be made into an N–to–2N decoder. Look at the circuit to the left. The control signals C1,C0 select the output to receive the input X. This is exactly equivalent to a decoder. In the circuit at right, the selected output gets the input, now called “Enable”. For the demultiplexers we use, the other outputs get a logic 1. We can fabricate an active low decoder. Page 12 of 13 pages