Designing FPGAs and ASICs: An Overview of IC Design and Implementation, Study Guides, Projects, Research of Digital Systems Design

Download Designing FPGAs and ASICs: An Overview of IC Design and Implementation and more Study Guides, Projects, Research Digital Systems Design in PDF only on Docsity! DESIGNING FPGAS & ASICS P f D B ldi Ph D SCHEMATIC HDL architecture behavior of control is if left_paddle then n_state <= hit_state elsif n_state <= miss_state end if; SYNTHESIS Overview of FPGAs and ASICs ro . on ou n, . .AND ORAND PHYSICAL LAYOUT PLACE & ROUTE Electrical & Computer Engineering University of Tennessee TEL: (865)-974-5444 FAX: (865)-974-5483 dbouldin@tennessee.edu ©2007 -- Don Bouldin 1 A VARIETY OF ICS ARE POSSIBLE ©2007 -- Don Bouldin 2 MASK CHARGES COST MILLIONS • According to SemaTech, a mask set for 65-nm costs $3 million. ©2007 -- Don Bouldin 5 http://www.tsmc.com/ THE COST PER GATE DECREASES AS THE DENSITY OF AN I C INCREASES. . • Microprocessors and other off- the-shelf LSI/VLSI chips are the most cost-effective because millions of gates are available in a single chip. ($0.0001/gate; 20,000 gates/pin) • SSI/MSI glue logic chips are the least cost-effective because only a few gates are available in a single chip. ($0.01/gate; 1-3 gates/pin) PENTIUM ©2007 -- Don Bouldin 6 SYSTEM FUNCTIONS ARE OFTEN SPLIT BETWEEN THE CPU AND AN ASIC • The most economical means of implementing logic functions is to use a Microprocessor Control Slow Inputs Slow Outputs Slow microprocessor. • When the microprocessor i t l t b t ASIC F t I t & FeedbackInputss oo s ow or oo usy o handle some fast inputs and outputs, an ASIC can as npu s Fast Outputsbe used to implement high-speed concurrent operations. ©2007 -- Don Bouldin 7 ECE 651 - 652 • ECE 651: – Perform custom IC design (but not submit for fab) – Compare manual design vs. automated tools – Study nanometer design issues (cross-talk, power) • ECE 652: – Extend our System-on-Chip platform – Design Testable ASIC for nanometer process – Optimize SoC at both synthesis and physical levels – Lectures on alternate weeks ©2007 -- Don Bouldin 10 PROGRAMMABLE LOGIC DEVICES ARE BEST FOR SMALL DESIGNS WITH I/O • Vendor prefabricates multiple sets of ANDs and ORs with programmable connections • User specifies connections to implement PLDs desired logic functions • Replaces 200 to 8 000 gates with single AND AND , package of 20-84 pins • Electrically programmable (and erasable) by AND AND OR the user one at a time within minutes • PC-based development system costs $1K ©2007 -- Don Bouldin 11 RECONFIGURABLE COMPONENTS ARE ADAPTABLE The internal logic and interconnect of a reconfigurable component (FPGA) may be specified by the user and changed at any time. CONTROL ARITHMETIC SIGNAL PROC. ©2007 -- Don Bouldin 12 STANDARD-HEIGHT CELL CHIPS CAN ALSO USE EMBEDDED RAM Space between rows for wiring can be varied as needed. ©2007 -- Don Bouldin 15 SPECIAL TECHNIQUES ARE USED FOR LAYOUT OF ANALOG CIRCUITS • Layouts use multi-gate fingers and common- centroid symmetry to improve matching of devices. • Poly2-Poly1 capacitors save space. • Switched-capacitor circuits replace large resistors. • Guard rings reduce noise. ©2007 -- Don Bouldin 16 SHARING MASK/WAFER COSTS ©2007 -- Don Bouldin 17 http://www.mosis.org/ http://www.ssec.honeywell.com/ CUSTOM IC DESIGN FLOW 1--SCHEMATIC 2--PRE-LAYOUT LOGIC SIMULATION 3 MANUAL LAYOUT 4 POST LAYOUT TRANS SIMULATION— -- - . ©2007 -- Don Bouldin 20 SEMI-CUSTOM DESIGN FLOW OF /DIGITAL FPGAS ASICS 1—HDL 2--PRE-SYNTHESIS SIMULATION CASE w IS WHEN "00" => y <= "1000" ; WHEN "01" => y <= "0100" ; 3 SYNTHESIS/AUTO LAYOUT WHEN "10" => y <= "0010" ; WHEN OTHERS => y <= "0001"; END CASE ; — 4--POST-LAYOUT SIMULATION ©2007 -- Don Bouldin 21 A HARDWARE DESCRIPTION LANGUAGE CAN BE SYNTHESIZED • The desired functionality and timing may be described using a hardware description language such as VHDL or Verilog and then synthesized into the structural level for a specified device. • Synthesis involves: (1) translation into Boolean equations, (2) optimization for area/delay, and then (3) i t FPGA ASIC (lib )mapp ng o a or process rary . • The physical level is then implemented automatically using a placement and routing program ©2007 -- Don Bouldin 22 . COLLABORATIVE DESIGN Designer#1 Designer#3 Designer#2 Designer#4 Collaborative Design of a System on Chip ©2007 -- Don Bouldin 25 - - http://www.cs.wright.edu/~tkprasad/courses/soc.html PROGRAMMABLE SYSTEM ON CHIP- - • CPU integrated inside the FPGA package – Replaces board with separate CPU and FPGA packages – Higher bandwidth and lower latency CPU f t l f ti– per orms con ro unc ons – CPU may lack floating-point capability Programmable System on Chip – - - (SoC) Platform – Can prototype ASIC SoC or an embedded system htt // ili / ©2007 -- Don Bouldin 26 p: www.x nx.com SYNTHESIS AND PHYSICAL DESIGN COUPLED • Wire load models were previously used by synthesis to predict layout capacitance accurately. However, these models are failing today. • Now that wire delays dominate gate delays in nanometer processes, synthesis must be coupled with physical floorplanning to achieve the desired timing goals . ©2007 -- Don Bouldin 27 http://www.synopsys.com/ SYSTEM-ON-CHIP REQUIRES CO DESIGN OF SW AND HW- • Traditional co-design uses C and SYSTEMC HDL separately. • Integration is performed on prototypes after using separate C HDL COMPILER/ SIMULATOR simulators with limited linkage. • SystemC is now being used for co- simulation at the behavioral level. COMPILER SYNTHESIS • The hardware portion is then automatically translated into HDL. • The same test bench is used at C SIMULATOR HDL SIMULATOR every level. htt // S t C / ©2007 -- Don Bouldin 30 p: www. ys em .org ECE 551-552 • ECE 551: – Pairs create project using VHDL – Simulate pre-synthesis and post-layout – Demonstrate using 200K-gate Xilinx FPGA S t 3 B d ith I/Oon par an oar w – Implement on screen only using Altera FPGA • ECE 552: – Team of 4 will create and reuse IP blocks – Programmable SoC design with DSP – Demonstrate using 1M-gate Virtex2-Pro/XUP – Lectures on alternate weeks ©2007 -- Don Bouldin 31 ECE 651 - 652 • ECE 651: – Perform custom IC design (but not submit for fab) – Compare manual design vs. automated tools – Study nanometer design issues (cross-talk, power) • ECE 652: – Extend our System-on-Chip platform – Design Testable ASIC for nanometer process – Optimize SoC at both synthesis and physical levels – Lectures on alternate weeks ©2007 -- Don Bouldin 32