Prof. Alexandridis' ece206 Course: Superscalars & Pipelining in Computer Architecture, Study notes of Electrical and Electronics Engineering

Download Prof. Alexandridis' ece206 Course: Superscalars & Pipelining in Computer Architecture and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! GWU: Prof. N. Alexandridis ece206: Detailed Outline Detailed Outline 1) BACKGROUND • Advances & state-of-the art • Improving system performance • Improving processor performance 2) SUPERSCALARS: INTRODUCTION • Superpipelining • Superscalars • Survey of recent processors • Fundamental limitations to ILP • Instruction and machine parallelism 3) SUPERSCALARS: SURVEY 4) PIPELINING I • Single- and multiple-clock pipelines • Conflicts • Load and branch delays • Performance metrics 5) HAZARDS • Structural hazards • Data hazards • Control hazards 6) PIPELINING II • Improving performance • Issues GWU: Prof. N. Alexandridis ece206: Detailed Outline 7) INSTRUCTION FETCH AND DECODE • Issues • Instruction buffers • Instruction queues • Instruction decode • Instruction windows/pools • Reorder buffers • Instruction alignment and merging • Branches and superscalar decoders (Implementing branches and hardware branch prediction will be covered later) 8) INSTRUCTION ISSUE POLICIES • In-order issue with in-order completion • In-order issue with out-of-order completion • Out-of-order issue with out-of-order completion •Survey of superscalar processor implementations 9) LONG LATENCY FUNCTIONAL UNITS • Multicycle functional units • Pipelined functional units • Hazards in long latency pipes • Superscalar examples GWU: Prof. N. Alexandridis ece206: Detailed Outline 17) BRANCH PREDICTION IN SUPERSCALARS • Branch prediction • Dynamic speculation • Reorder buffers, reservation stations • Dynamic disambiguation of memory references • Tomasulo with Load/Store buffers 18) SOFTWARE SOLUTIONS TO CONTROL HAZARDS • Branch spreading • Scheduling the branch delay slot • Branch folding •Software (static) branch prediction 19) LOOP UNROLLING • Loop unrolling in scalars • Scheduling across branches • Floating point loop hazards • Compiler code movement • Loop unrolling in superscalars •List scheduling the unrolled loop 20) TRACE SCHEDULING • Software scheduling of delayed branches • Examples of trace scheduling in superscalars • Using “compensation code” GWU: Prof. N. Alexandridis ece206: Detailed Outline 21) SOFTWARE PIPELINING • Definitions • Examples • Limits of superscalars • Loop unrolling in VLIW • Software pipelining in superscalars • Scheduling for software pipelining • Register renaming •Global code motion 22) LOAD/STORE ARCHITECTURES • Introduction •Survey on current processor implementations 23) INTERRUPT AND EXCEPTION HANDLING • Introduction •Survey on Current Processor Implementations 24) VLIW and EPIC 25) MULTITHREADING • Multithreading processors • Simultaneous multithreading • Multiprocessor processors 26) CONCLUSIONS