Download EECS 270: Lab 5 - Understanding Latches and Flip-Flops and more Lab Reports Electrical and Electronics Engineering in PDF only on Docsity! LAB 5Prof. Jenkins and Prof. MazumdeLatches and Flip-Flops You will learn how latches and flip-flops work. You will also learn how to use a few more of the simulator’s features.1.0 Overview Latches and flip-flops are the primitive storage devices in sequential circuits. In this experiment you will study their functional and temporal behavior and develop some insights about sequential circuit operation in general. 2.0 Preparation You must be thoroughly familiar with the material in Sec. 7.2 of Wakerly. 3.0 Design Specification Use the schematic editor to create the circuit shown in Figure 6. It consists of a parallel connection of four storage elements: an SR latch, a clocked SR latch, a D latch and a D master-slave flip-flop. The schematics for these “macros” are shown in Fig. 2. The S, R, D, and C inputs of these devices should be connected, respectively, to the D0, D1, D2, and D3 lines of the PC parallel port. The true and complemented outputs Qi, QiBAR (i = 1, 2, 3, 4) should be connected to the indicated segments of the left and right LED dis- plays; this makes it easy to quickly determine the state of each device. What you need to do is to analyze each of these devices using the simulator. First, you will determine the device’s functional behavior by performing unit-delay simulation. Next, you will implement the circuit, extract its actual delays, and perform a timing sim- ulation to derive some of the devices’ temporal parameters. In the lab, you will confirmr EECS 270: Introduction to Logic Design 5-1 University of Michigan–Fall 2000 Notes LAB 5: Latches and Flip-Flopsthe simulation results by stimulating each of the devices from the PC parallel port and observing its output on the LED indicators. 4.0 Notes • Make sure you add the KEEP attribute to all nets; this will insure that their driving gates are not collapsed (optimized away) by the synthesis tools, and makes it possi- ble to back-annotate the estimated delays necessary for timing simulation. • Set the simulation precision to 100ps (0.1ns). This setting controls the minimum resolvable time in the simulator; it also controls the number of significant digits dis- played in the device delay table (accessed through the simulator’s Device->Edit Timing Specification). • Note that the simulator maps your gates to gates in the simprims library. These gates have types whose labels start with an “x_” prefix; the extracted delays are attached to FIGURE 6. Top-level schematic of latch/flip-flop circuit Q1 Q2 Q1BAR Q2BAR LEFT LED Q3 Q4 Q3BAR Q4BAR RIGHT LED5-2 EECS 270: Introduction to Logic Design Prof. Jenkins and Prof. Mazumder University of Michigan–Fall 2000
