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Digital Arithmetic and Arithmetic Circuits, Lecture notes of Engineering

System level design of digital logic circuits using hardwired and programmable logic devices. ROMs, PROMs, and PLAs. Synchronous and asynchronous circuit design and analysis

Typology: Lecture notes

2021/2022

Available from 12/22/2022

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Download Digital Arithmetic and Arithmetic Circuits and more Lecture notes Engineering in PDF only on Docsity! Digital Arithmetic 1 Digital Arithmetic and Arithmetic Circuits (Chapter 7 Dueck) • Signed Binary Number: A binary number of fixed length whose sign (+/–) is represented by one bit (usually MSB) and its magnitude by the remaining bits. • Unsigned Binary Number: A binary number of fixed length whose sign is not specified by a bit. All bits are magnitude and the sign is assumed +. Signed/Unsigned Binary Numbers Digital Arithmetic 2 Digital Arithmetic and Arithmetic Circuits (Chapter 7 Dueck) • Sum: – Result of an Addition Operation of two (or more) binary numbers (operands). • Carry: – A digit (or bit) that is carried over to the next most significant bit during an n-Bit addition operation. • The carry bit is a 1 if the result was too large to be expressed in n bits. Unsigned Binary Arithmetic Digital Arithmetic 5 Digital Arithmetic and Arithmetic Circuits (Chapter 7 Dueck) Signed Binary Numbers – 2 • True-Magnitude Form: – A form of signed binary whose magnitude bits are the TRUE binary form (not complements). Digital Arithmetic 6 Digital Arithmetic and Arithmetic Circuits (Chapter 7 Dueck) True-Magnitude Form • 5-Bit Numbers Negative Sign (S = 1) • +25 = 011001 (Note sign bit (MSB) Sign = 0) • –25 = 111001 (Same as +25 with sign = 1) • +12 = 001100 • –12 = 101100 Digital Arithmetic 7 Digital Arithmetic and Arithmetic Circuits (Chapter 7 Dueck) Signed Binary Addition (8-Bit) • Signed Addition Positive (S = 0) • Similar to binary addition with a sign bit. 1001 0110 1011 0100 75 1110 0001 30 Digital Arithmetic 10 Digital Arithmetic and Arithmetic Circuits (Chapter 7 Dueck) • Used in MPU (PC) Arithmetic 2’s Complement Form 1000 1011 1 0111 1011 72- 1000 0100 72 0111 1011 1 0110 1100 57- 1001 0011 57 Digital Arithmetic 11 Digital Arithmetic and Arithmetic Circuits (Chapter 7 Dueck) • Add 2’s Complement to Minuend. ResultfromBitCarryDiscard 111100001 111110111111101165 000001010000010180 ?6580 2’s Complement Subtraction 11111011 11110101165 0001010065 65 of compliment s2' Digital Arithmetic 12 Digital Arithmetic and Arithmetic Circuits (Chapter 7 Dueck) • 2’s Complement Negative Result (65 – 80 = ?) Negative Result Example )(15 1111 0000 )15(Result Final 1 1 Add 1110 0000Invert 0001 1111 0000 011 1 C.) s(2' 0000 1011 80- 0001 0100 0001 0100 65 1010
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