Advantages of CMOS over NMOS in Digital Electronics - Prof. Aurangzeb Khan, Study notes of Electrical and Electronics Engineering

Download Advantages of CMOS over NMOS in Digital Electronics - Prof. Aurangzeb Khan and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! 1 After mid-term review EE 334 Digital electronics NMOS inverter CMOS inverter NMOS logic gates CMOS logic gates NMOS transmission gates CMOS transmission gates Sequential logic circuits NMOS flip flop CMOS flip flop J K flip flop Design is the heart of engineering. Throughout the course designing concepts have been emphasized. MOS Digital Circuits Chapter 16 • In the late 70s as the era of LSI and VLSI began, NMOS became the fabrication technology choice. • Later the design flexibility and other advantages of the CMOS were realized, CMOS technology then replaced NMOS at all level of integration. • The small transistor size and low power dissipation of CMOS circuits, demonstration principal advantages of CMOS over NMOS circuits. NMOS Inverter • For any IC technology used in digital circuit design, the basic circuit element is the logic inverter. • Once the operation and characterization of the inverter circuits are thoroughly understood, the results can be extended to the design of the logic gates and other more complex circuits. + + VGS=V RD =VDD=VDS NMOS Inverter (resistor load) NMOS Inverter with Enhancement Load • This basic inverter consist of two enhancement-only NMOS transistors and is much more practical than the resister loaded inverter, which is thousand of times larger than a MOSFET. 2 NMOS Inverter with Enhancement Load VO,, max= VOH =VDD-VTNL NMOS Inverter with Depletion Load • This is an alternate form of the NMOS inverter that uses an enhancement- depletion MOSFET load device with gate and source terminal connected. • This inverter has the advantage of VO= VDD, as well as more abrupt VTC transition region even though the W/L ratio for the output MOSFET is small. • The term depletion mode means that a channel exists even with zero gate voltage. VT Characteristics of NMOS Inverter with Depletion Load The Figure demonstrate in present configuration more abrupt VTC transition region can be achieved even though the W/L ratio for the output MOSFET is small. 1160µW 825µW 200µW Transient Analysis of NMOS inverters • The source of capacitance CT2 and CT3 are the transistor input capacitances and parasitic capacitances due to interconnect lines between the inverter stages. • The constant current over a wide range of VDS provided by the depletion load implies that this type of inverter switch a capacitive load more rapidly than the other two types inverter configurations. The rate at 5 CMOS inverter static power • Static power consumption: – Static current: in CMOS there is no static current as long as Vin < VTN or Vin > VDD+VTP – Leakage current: determined by “off” transistor – Influenced by transistor width, supply voltage, transistor threshold voltagesVDD VI<VTN Ileak,n Vcc VDD Ileak,p Vo(low) VDD Dynamic Power Dissipation and Total Energy Stored in the CMOS Device Case II: when the input is high and out put is low: During switching all the energy stored in the load capacitor is dissipated in the NMOS device because NMOS is conducting and PMOS is in cutoff mode. The energy dissipated in the NMOS inverter can be written as, The total energy dissipated during one switching cycle is, The power dissipated in terms pf frquency can be written as 2 2 1 DDLN VCE = 222 2 1 2 1 DDLDDLDDLNPT VCVCVCEEE =+=+= 2 DDLT T T VfCfEPt EPtPE ⇒=⇒=⇒= This implied that the power dissipation in the CMOS inverter is directly proportional to switching frequency and VDD2 Dynamic capacitive power • Formula for dynamic power: • Observations – Does not (directly) depend on device sizes – Does not depend on switching delay – Applies to general CMOS gate in which: • Switched capacitances are lumped into CL • Output swings from Gnd to VDD • Input signal approximated as step function • Gate switches with frequency f fVCP DDLdyn 2= Dynamic short-circuit power • Short-circuit current flows from VDD to Gnd when both transistors are on saturation mode • Plot on VTC curve: VCC VCCVin Vout ID Imax Imax: depends on saturation current of devices Inverter power consumption • Total power consumption fVCP PP PPPP CCLtot dyntot statscdyntot 2≅ ≅ ++= Power reduction • Reducing dynamic capacitive power: – Lower the voltage! • Quadratic effect on dynamic power – Reduce capacitance • Short interconnect lengths • Drive small gate load (small gates, small fan-out) – Reduce frequency • Lower clock frequency - • Lower signal activity fVCP DDLdyn 2= 6 Power reduction • Reducing short-circuit current: – Fast rise/fall times on input signal – Reduce input capacitance – Insert small buffers to “clean up” slow input signals before sending to large gate • Reducing leakage current: – Small transistors (leakage proportional to width) – Lower voltage Concept of Noise Margins NML=VIL-VOL (noise margin for low input) NMH=VOH-VIH (noise margin for high input) NML=VIL-VOLU (noise margin for low input) NMH=VOHU - VIH (noise margin for high input) VI CMOS Logic Circuits Large scale integrated CMOS logic circuits such as watched, calculators, and microprocessors are constructed by using basic CMOS NOR and NAND gates. Therefore, understanding of these basic gates is very important for the designing of very large scale integrated (VLSI) logic circuits. 7 CMOS NOR gate CMOS NOR gate can be constructed by using two parallel NMOS devices and two series PMOS transistors as shown in the figure. In the CMOS NOR gate the output is at logic 1 when all inputs are low. For all other possible inputs, output is low or at logic 0. 8 Design considerations of CMOS NOR and NAND symmetrical gate? • In order to obtained symmetrical switching times for the high-to-low and low-to-high output transitions, the effective conduction (design) parameters of the composite PMOS and composite NMOS device must be equal. For the CMOS NOR gate we can write as, KCN=KCP By recalling effective channel width and effective channel length concept we can effective conduction parameter for NMOS and PMOS for a CMOS NOR as, Since K´n~2K´p p p N n L WK L WK      ′=     ′ 22 2 2 pN L W L W      =      2 22 NP L W L W      =      8or For asymmetrical case switching time is longe NP L W L W      =      2 1 For NAND gate: Why we need symmetrical Gates? Transmission Gates • Characteristics of NMOS transmission gate. Dynamic and static conditions. • Characteristics of CMOS Transmission gate. • In CMOS logic gate that a logic ‘1’ is transmitted unattenuated through the CMOS transmission gate in contrast to the NMOS transmission gate. • Sequential Logic circuits; Characteristics of Dynamic Shift Registers and CMOS dynamic shift register. 7 7 Characteristics of NMOS transmission gate If φ=VDD, VI=VDD, and initially, the output V0 is 0 and capacitance CL is fully discharged. Under these conditions, the terminal ‘a ‘acts as the drain because its bias is VDD, and terminal ‘b’ acts as the source because its bias is 0. The gate to source voltage can be written as VGS=φ-VO or VGS= VDD-VO As CL charges up and Vo increases, the gate to source voltage decreases. When the gate to source voltage VGS become equal to threshold voltage VTN, the capacitance stop charging and current goes to zero. This implies that the VO=VO(max) when VGS=VTN Or VO(max) = VDD-VTN d S G This implies that output voltage never will be equal to VDD. ; rather it will be lower by VTN. This is one of the disadvantage of an NMOS transmission gate when VI=high Why NMOS transmission gate does not remain in a static condition? • The reverse leakage current due to reverse bias between terminal b and ground begins to discharge the capacitor, and the circuit does not remain in a static condition. VDD-Vt source draingate CMOS Transmission Gate • A CMOAS transmission gate can be constructed by parallel combination of NMOS and PMOS transistors, with complementary gate signals. • The main advantage of the CMOS transmission gate compared to NMOS transmission gate is to allow the input signal to be transmitted to the output without the threshold voltage attenuation. CMOS transmission gate Characteristics of a CMOS Transmission gate (Cont.) • When VO=VDD-VTN, VGSN=VTN, the NMOS transmission gate cuts off and IDN=0. However, PMOS transistor continue to conduct, because VGSP of the PMOS is a constant (VGSP=VDD). In PMOS transistor IDP=0, when VSDP=0, which would be possible only, if, VO = VI = 5V This implies that a logic ‘1’ is transmitted unattenuated through the CMOS transmission gate in contrast to the NMOS transmission gate. Drain source source Drain d S G NMOS transmission gate CMOS transmission gate remains in a dynamic condition. • If VO=VDD, then NMOS substrate to terminal ‘b’ pn junction is reverse biased and capacitor CL can discharge. • If VO=0, then the PMOS terminal c-to-substrate pn junction is reverse biased and capacitance CL can be charge to a positive voltage. • This implies that the output high or low of CMOS transmission gate circuit do not remain constant with time (dynamic behavior). Sequential Logic circuits • The logic circuits considered thus far are called combinational logic circuits. Their output depend only on the present value of input. This implies that these circuit do not have memory. • Another class of the logic circuit that incorporate memory are called sequential logic circuits; that is, their output depend not only the present value of the input, but also on the previous history of inputs. Shift registers and flip-flops are typical examples of such circuits. 10 Close loop i1 = i2 V0=V1-i2R2=0 - (VI/R1)R2 If the op amp open loop gain is finite (non ideal op amp) 11 i1 i1 i1=VI/R1, this current also flow through the capacitor , causing charge to accumulate on VC. At time t, the charge Q at the capacitance equal to dtti t )( 0 1∫ Because i=Q/t and the voltage across the capacitor is dtti c t )(1 0 1∫ Because Q=CV. If initial voltage (t=0) on C is denoted VC dtti c VtV t CC )( 1)( 0 1∫+= Now the output voltage VO=-VC(t) dtti C VV t CO )( 1 0 1∫−−= dttVCRVV t ICO )( 1 0 ∫−−=In terms of the voltage Thus the circuit provides an output voltage that is proportional to time integral of the input. 12 We know the current I is the rate of change of charge i i i=dQ/dt, also Q=CV dt dvCvC dt di II 11 )( == Since A is a virtual ground A d R dt dvCiRv IO )( . 22      −=−= dt tdvCRv IO )( 12−= There are number of ways to solve this problem; perhaps the easiest is using the principle of superposition and virtual short concept. To apply superposition we first reduce VI2=0 What is the condition under which this circuit will act as a difference amplifier? Let VI1=VI2 ⇒ VO=0 ⇒ Which is clearly that of a difference amplifier with a gain of R2/R1 Passive and active filters • Filters are building blocks of communication and instrumentations. • The oldest technology based on inductors and capacitors are called passive LC filters, which are incompatible with any of the modern techniques for assembling electronic systems. • Active-RC filters utilize op amp together with resistors and capacitors. • At present, the most viable approach for realizing fully integrated monolithic filters is the switch capacitance techniques. 15 • An electronic oscillator may be define in any one of the following four ways: i) It is a circuit which convert dc energy into ac energy at a very high frequency ii) It is an electronic source of alternating current or voltage having sine, square or sawtooth or pulse shapes iii) It is circuit which generates an ac output signals without requiring any externally applied input signal. iv) It is an unstable amplifier. Classification of Oscillators • Electronic oscillators may be broadly divided into following two groups: i) sinusoidal (or harmonic) oscillators-which produce an output having sine wave form ii) non- sinusoidal (or relaxation) oscillators- they produce an output which has square, rectangular or sawtooth wave form, employ circuit building blocks known as multivibrators. oscillations 16 The oscillation frequency of the phase shift amplifier is given by