Hardware Description Languages: An Overview of Verilog and VHDL, Study notes of Electrical and Electronics Engineering

Download Hardware Description Languages: An Overview of Verilog and VHDL and more Study notes Electrical and Electronics Engineering in PDF only on Docsity! Copyright © 2007 Elsevier <1> Chapter 4 : Hardware Descriptive Languages Digital Logic Design James E. Stine, Jr. Portions of slides taken from Digital Design and Computer Architecture D. M. Harris and S. L. Harris, Elsevier, 2007 Copyright © 2007 Elsevier <2> Chapter 4 :: Topics • Introduction • Combinational Logic • Structural Modeling • Sequential Logic • More Combinational Logic • Finite State Machines Copyright © 2007 Elsevier <5> Verilog Modules Two types of Modules: – Behavioral: describe what a module does – Structural: describe how a module is built from simpler modules a b y c Verilog Module Copyright © 2007 Elsevier <6> Behavioral Verilog Example module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Verilog: Copyright © 2007 Elsevier <7> Behavioral Verilog Simulation module example(input a, b, c, output y); assign y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Verilog: Copyright © 2007 Elsevier <10> Structural Modeling - Hierarchy module and3(input a, b, c, output y); assign y = a & b & c; endmodule module inv(input a, output y); assign y = ~a; endmodule module nand3(input a, b, c output y); wire out; // internal signal and3 andgate(a, b, c, out); // instance of and3 inv inverter(out, y); // instance of inverter endmodule Copyright © 2007 Elsevier <11> Bitwise Operators module gates(input [3:0] a, b, output [3:0] y1, y2, y3, y4, y5); /* Five different two-input logic gates acting on 4 bit busses */ assign y1 = a & b; // AND assign y2 = a | b; // OR assign y3 = a ^ b; // XOR assign y4 = ~(a & b); // NAND assign y5 = ~(a | b); // NOR endmodule // single line comment /*…*/ multiline comment Copyright © 2007 Elsevier <12> Reduction Operators module and8(input [7:0] a, output y); assign y = &a; // &a is much easier to write than // assign y = a[7] & a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] & a[0]; endmodule Copyright © 2007 Elsevier <15> Precedence ternary operator?: OR, XOR|, ~| XOR, XNOR^, ~^ AND, NAND&, ~& equal, not equal==, != comparison<, <=, >, >= arithmetic shift<<<, >>> shift<<, >> add,sub+, - mult, div, mod*, /, % NOT~ Defines the order of operations Highest Lowest Copyright © 2007 Elsevier <16> Numbers 00…010101042decimalUnsized42 10101011171hexadecimal88’hAB 10001034octal66’o42 1106decimal33’d6 10101011171binary88’b1010_1011 000000113binary88’b11 00…00113binaryunsized‘b11 1015binary33’b101 StoredDecimal Equivalent Base# BitsNumber Format: N'Bvalue N = number of bits, B = base N'B is optional but recommended (default is decimal) Copyright © 2007 Elsevier <17> Bit Manipulations: Example 1 assign y = {a[2:1], {3{b[0]}}, a[0], 3’b100_010}; // if y is a 12-bit signal, the above statement produces: y = a[2] a[1] b[0] b[0] b[0] a[0] 1 0 0 0 1 0 // underscores (_) are used for formatting only to make it easier to read. Verilog ignores them. Copyright © 2007 Elsevier <20> Delays module example(input a, b, c, output y); wire ab, bb, cb, n1, n2, n3; assign #1 {ab, bb, cb} = ~{a, b, c}; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3; endmodule Copyright © 2007 Elsevier <21> Delays module example(input a, b, c, output y); wire ab, bb, cb, n1, n2, n3; assign #1 {ab, bb, cb} = ~{a, b, c}; assign #2 n1 = ab & bb & cb; assign #2 n2 = a & bb & cb; assign #2 n3 = a & bb & c; assign #4 y = n1 | n2 | n3; endmodule Copyright © 2007 Elsevier <22> Sequential Logic • Verilog uses certain idioms to synthesize into latches, flip-flops and FSMs • Other coding styles may simulate correctly but produce incorrect hardware Copyright © 2007 Elsevier <25> module flopr(input clk, input reset, input [3:0] d, output reg [3:0] q); // synchronous reset always @ (posedge clk) if (reset) q <= 4'b0; else q <= d; endmodule Resettable D Flip-Flop q[3:0] q[3:0] [3:0] d[3:0] [3:0] reset clk [3:0] Q[3:0] [3:0] D[3:0] R Copyright © 2007 Elsevier <26> module flopr(input clk, input reset, input [3:0] d, output reg [3:0] q); // asynchronous reset always @ (posedge clk, posedge reset) if (reset) q <= 4'b0; else q <= d; endmodule Resettable D Flip-Flop q[3:0] R q[3:0] [3:0] d[3:0] [3:0] reset clk [3:0] Q[3:0] [3:0] D[3:0] Copyright © 2007 Elsevier <27> module flopren(input clk, input reset, input en, input [3:0] d, output reg [3:0] q); // asynchronous reset and enable always @ (posedge clk, posedge reset) if (reset) q <= 4'b0; else if (en) q <= d; endmodule D Flip-Flop with Enable Copyright © 2007 Elsevier <30> Rules for Signal Assignment • Use always @ (posedge clk) and nonblocking assignments to model synchronous sequential logic always @ (posedge clk) q <= d; // nonblocking • Use continuous assignments to model simple combinational logic. assign y = a & b; • Use always @ (*) and blocking assignments to model more complicated combinational logic where the always statement is helpful. • Do not make assignments to the same signal in more than one always statement or continuous assignment statement. Copyright © 2007 Elsevier <31> Finite State Machines (FSMs) CLK M Nk knext state logic output logic inputs outputs state next state • Three blocks: – next state logic – state register – output logic Copyright © 2007 Elsevier <32> The double circle indicates the reset state FSM Example: Divide by 3 S0 S1 S2