Digital Logic Lab Report: Measuring Gate Delays and Static Logic in EECS 40 Spring 2003, Lab Reports of Electrical and Electronics Engineering

Download Digital Logic Lab Report: Measuring Gate Delays and Static Logic in EECS 40 Spring 2003 and more Lab Reports Electrical and Electronics Engineering in PDF only on Docsity! EECS 40 Spring 2003 KH Aschenbach, B Muthuswamy, WG Oldham Digital Logic: Lab Report 1. Draw the layout of the 4-inverter chain using the Quad NAND IC. Show the actual physical layout of the circuit – “top view” – on the breadboard. Also show the internal wiring of the breadboard. 2. Construct the inverter chain, using a wire to apply either Vdd=5V=logic 1 or Vss=0V=logic 0 to the chain input. Using the scope, verify the logic states within the chain. Repeat for Vdd=2V. Next, setup the function generator to provide a 1kHz square wave to the input and verify the switching of all the inverters in the chain. 3. Set the function generator to input a 1kHz square. Measure the gate delays through 1,2,3,4 gates at Vdd=5V, then Vdd=2V. Be sure to set the function generator VPP and VDC for different Vdd. To switch between HL and LH transitions, switch the trigger edge direction. For convenience, set Time Ref to Left. Vdd=5V 1 gate 2 gates 3 gates 4 gates tpHL, Output tpLH, Output Average tpavg Vdd=2V 1 gate 2 gates 3 gates 4 gates tpHL, Output tpLH, Output Average tpavg 1