Download Digital Signals-Introduction to Microelectronic Circuits-Lecture 26 Slides-Electrical Engineering and more Slides Microelectronic Circuits in PDF only on Docsity! 1 Lecture 26, Slide 1EECS40, Fall 2003 Prof. King Lecture #26 ANNOUNCEMENTS • Extra Office Hours this week: – Prof. King: Thursday 10/30 12-2 PM – Steve: Friday 10/31 12-2 PM – Farhana: • Review session: Friday 10/31 2-4 PM, 120 Latimer OUTLINE • Logic functions • NMOS logic gates • The CMOS inverter Reading • Schwarz & Oldham: Chapters 11.2, 15.3 • Rabaey et al.: Chapter 5.2 Lecture 26, Slide 2EECS40, Fall 2003 Prof. King Digital Signals • For a digital signal, the voltage must be within one of two ranges in order to be defined: • Positive Logic: – “low” voltage ≡ logic state 0 – “high” voltage ≡ logic state 1 “1” “0” VOH VIH VIL VOL undefined region increasing voltage VDD 0 Volts 2 Lecture 26, Slide 3EECS40, Fall 2003 Prof. King Logic Functions, Symbols, & Notation “NOT” F = A TRUTH NAME SYMBOL NOTATION TABLE FA 111 001 010 000 FBA “OR” F = A+BFAB 01 10 FA 111 101 110 000 FBA “AND” F = A•BFA B Lecture 26, Slide 4EECS40, Fall 2003 Prof. King “NOR” F = A+B 011 101 110 000 FBA “NAND” F = A•BFAB 011 101 110 100 FBA “XOR” (exclusive OR) F = A + BFA B FAB 011 001 010 100 FBA 5 Lecture 26, Slide 9EECS40, Fall 2003 Prof. King Disadvantages of NMOS Logic Gates • Large values of RD are required in order to – achieve a low value of VOL – keep power consumption low Large resistors are needed, but these take up a lot of space. • One solution is to replace the resistor with an NMOSFET that is always on. Lecture 26, Slide 10EECS40, Fall 2003 Prof. King The CMOS Inverter: Intuitive Perspective VDD Rn VIN = VDD CIRCUIT SWITCH MODELS VDD Rp VIN = 0 V VOUT VOUT VOL = 0 V VOH = VDD Low static power consumption, since one MOSFET is always off in steady state VDD VIN VOUT S D G G S D 6 Lecture 26, Slide 11EECS40, Fall 2003 Prof. King CMOS Inverter Voltage Transfer Characteristic VIN VOUT VDD VDD0 0 N: off P: lin N: lin P: off N: lin P: sat N: sat P: lin N: sat P: sat VDD VIN VOUT S D G G S D A B D E C Lecture 26, Slide 12EECS40, Fall 2003 Prof. King CMOS Inverter Load-Line Analysis VOUT=VDSn IDn=-IDp 0 VDD VIN VOUT IDn=-IDp – V GSp =V IN -V DD + VIN = VDD + VGSp increasing VIN increasing VIN VIN = 0 V VIN = VDD VDD VOUT = VDD + VDSp VDSp = 0VDSp = - VDD – VDSp=VOUT-VDD + 0 7 Lecture 26, Slide 13EECS40, Fall 2003 Prof. King VOUT=VDSn IDn=-IDp 0 VDD 0 CMOS Inverter Load-Line Analysis: Region A VDD VIN VOUT IDn=-IDp – V GSp =V IN -V DD + – VDSp=VOUT-VDD + VIN ≤ VTn Lecture 26, Slide 14EECS40, Fall 2003 Prof. King VOUT=VDSn IDn=-IDp 0 VDD 0 CMOS Inverter Load-Line Analysis: Region B VDD VIN VOUT IDn=-IDp – V GSp =V IN -V DD + – VDSp=VOUT-VDD + VDD/2 > VIN > VTn
