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CS 152 Midterm II: Computer Architecture - UC Berkeley, Exams of Computer Architecture and Organization

The cs 152 midterm ii exam for the computer architecture and engineering course at the university of california at berkeley. The exam covers topics such as virtual memory, i/o, and caches. Students are required to answer questions related to address translation, disk performance analysis, and cache configurations. The exam includes a tlb state table, memory accesses, and cache configurations for evaluation.

Typology: Exams

2012/2013

Uploaded on 04/02/2013

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Download CS 152 Midterm II: Computer Architecture - UC Berkeley and more Exams Computer Architecture and Organization in PDF only on Docsity! University of California at Berkeley College of Engineering Computer Science Division - EECS CS 152 D. Patterson & R. Yung Fall 1995 Computer Architecture and Engineering Midterm II You may use two pages of notes. You have 180 minutes. Please write your name on this cover sheet and also at the top left of each page. The point value of each question is indicated in brackets after it. Please show your work. Write neatly and be well organized. Good luck! Your Name: SID Number: Discussion TA(s): Problem Score 1 / 27 2 / 13 3 / 30 4 / 20 Total / 90 Your Name: 1 Question 1: Virtual Memory An eight-entry direct-mapped TLB is implemented in the current design. Both the virtual and physical addresses are 32 bits wide, and page size is 4kB. Address translation is performed by this TLB for every memory access. NOTE: All addresses are given in hexadecimal. a) Label the virtual and physical address fields used in address translation. [4 pt] Virtual Address 31 12 11 0 Physical Address 31 12 11 0 -1 for having VPN=[31:13], PFN=[12:0] -2 for all other mistakes Virtual Page Number (VPN) Offset Physical Frame Number (PFN) Offset Your Name: 4 Question 2: I/O A 1993 3.5 inch IBM disk rotates at 4318 revolutions-per-minute (RPM), has a ran- dom seek time of 11ms, transfers at 4 MB/s, has a capacity of 1 GB, and the mean-time-to-failure (MTTF) is 400,000 hours. The SCSI controller overhead is 2ms. A 1995 3.5 inch IBM disk rotates at 7200 RPM, has a random seek time of 8ms, trans- fers at 12 MB/s, has a capacity is 4.2 GB, and the MTTF is 1,000,000 hours. The SCSI controller overhead today is 1ms. a) On average, how much faster is the new disk than the old disk for a read of 4 kB assuming random seeks? Assume the disks are idle so that there is no waiting time. [4 pt] b) If the actual seek time is 25% of the random seek, how much faster is the new disk now? [4 pt] c) Now assume the read size is 1 megabyte, with seeks being 25% of random time. How much faster is the new disk? [4 pt] d) What does this performance change in just two years suggested in the design of computer sys- tems? [1 pt] For a, b, c: Get wrong speedup consistently: -1 Leave off adapter overhead: -3 Leave off rotation time: -3 Off by factor of 100: -2 Poss. ans. for d: Since disks have become 1.69 times faster for small transfers and 2.89 times faster for large transfers in the last two years, it suggests that larger disk transfers will be encouraged in the future (e.g., larger page sizes). t tSEEK 1 2 --tROT tOH xfersize BW --------------------+ + += tOLD 11ms 60 secmin--------- 1000 ms sec -------× 2 4318 revmin---------× ------------------------------------ 2ms 4kB 1000mssec-------× 4MBsec-------- 1000 kB MB --------× ---------------------------------+ + + 20.95ms= = tNEW 8ms 60 secmin--------- 1000 ms sec -------× 2 7200 revmin---------× ------------------------------------ 1ms 4kB 1000mssec-------× 12MBsec-------- 1000 kB MB --------× ------------------------------------+ + + 13.50ms= = Speedup tOLD tNEW ---------- 20.95ms 13.50ms -------------------- 1.55timesfaster= = = tOLD 0.25 11ms× 60 secmin--------- 1000 ms sec -------× 2 4318 revmin---------× ------------------------------------ 2ms 4kB 1000mssec-------× 4MBsec-------- 1000 kB MB --------× ---------------------------------+ + + 12.70ms= = tNEW 0.25 8ms× 60 secmin--------- 1000 ms sec -------× 2 7200 revmin---------× ------------------------------------ 1ms 4kB 1000mssec-------× 12MBsec-------- 1000 kB MB --------× ------------------------------------+ + + 7.50ms= = Speedup 12.70ms 7.50ms -------------------- 1.69timesfaster= = tOLD 0.25 11ms× 60 secmin--------- 1000 ms sec -------× 2 4318 revmin---------× ------------------------------------ 2ms 1MB 1000mssec------× 4MBsec-------- -----------------------------------+ + + 261.70ms= = tNEW 0.25 8ms× 60 secmin--------- 1000 ms sec -------× 2 7200 revmin---------× ------------------------------------ 1ms 1MB 1000mssec-------× 12MBsec-------- -----------------------------------+ + + 90.50ms= = Speedup 261.70ms 90.50ms ----------------------- 2.89timesfaster= = Your Name: 5 Question 3: Caches In your first job out of school, you are given the task of evaluating the performance of four data cache designs (shown inTable 4). The best one will be incorporated in the next-generation proces- sor design. The caches are accessed with 16-bit virtual addresses. a) For each cache configuration, fill in the fields in Table 5. (Entry E gives an example for a 4B, direct-mapped, 1B block size, no sub-block, no write-allocate cache.) [8 pt] Left two columns: -1/2 pt. for every wrong answer Right three columns: -1/2 pt. for every wrong answer up to -1 per row Table 4: Four cache configurations Capacity Associativity Block Size Sub-block Size Write Policy A 32B direct-mapped 8B 4B no write allocate B 32B 2-way 8B none no write allocate C 32B direct-mapped 8B none write allocate D 32B 2-way 8B 4B write allocate Table 5: Fields in the caches cache tag cache index # of valid bit(s) per block total # blocks in cache # sub- blocks per block A VA[15:5] VA[4:3] 2 4 2 B VA[15:4] VA[3] 1 4 none C VA[15:5] VA[4:3] 1 4 none D VA[15:4] VA[3] 2 4 2 E VA[15:2] VA[1:0] 1 4 none Your Name: 6 b) Here is a sequence of ten one-byte memory references (in hex) to the caches: R 0x0, W 0x4, R 0x6, R 0x20, R 0x25, W 0x27, W 0x1, R 0x23, R 0x3, R 0x4. NOTE: R - read access, W - write access Fill in hit or miss for each memory references for the four cache configurations. Compute the final cache miss rates. NOTE: each cache starts out empty. [22 pt] Results for the above example, cache E, are shown in the last column. -1/2 pt. for every wrong answer Table 6: Results of the cache references references cache configurations A B C D E 0x00 R miss miss miss miss miss 0x04 W miss hit hit miss miss 0x06 R miss hit hit hit miss 0x20 R miss miss miss miss miss 0x25 R miss hit hit miss miss 0x27 W hit hit hit hit miss 0x01 W miss hit miss hit miss 0x23 R hit hit miss hit miss 0x03 R miss hit miss hit miss 0x04 R miss hit hit hit miss miss rate (%) 80% 20% 50% 40% 100%
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