Download Microelectronic Devices and Circuits - EECS105 Final Exam and more Exams Microeconomics in PDF only on Docsity! Microelectronic Devices and Circuits - EECS105 Final Exam Wednesday, December 9, 1998 Costas J. Spanos Total: 100 points MOS Device Data MUnCox = 50 uA/V^2, MUpCox = 25 uA/V^2, VTn = -VTp = 1 V, LAMBDAn = LAMBDAp = 0.1V^-1 um (i.e. LAMBDA is 0.1 V^-1 when L = 1 um, and is proportional to 1/L), Cox = 2.3 fF/um^2, Cjn = 0.1 fF/um^2, Cjp = 0.3 fF/um^2, Cjswn = 0.5 fF/um, Cjswp = 0.35 fF/um, Covn = 0.5 fF/um = Covp npn Bipolar Device Data Is = 10^-17 A, BETA = 100, Va = 25 V, TAUf = 50 ps, Cje = 15 fF, Cmu = 10 fF Problem #1 of 4: Answer each question briefly and clearly (3 points each, total 24) a) What type of electrical current (drift or diffusion?) and what type of carriers (holes or electrons?) flows between the source and the drain of an n-channel MOS transistor? b) Where is the maximum absolute electric field within an MOS capacitor in depletion, made of Al, SiO2, and p-type doped Silicon? (Mark your answer on the graph and give brief explanation) c) What are the noise margins of a dynamic logic gate that employs an n-channel logic network? EE105, Final, Fall 1998 Microelectronic Devices and Circuits - EECS105 Final Exam Wednesday, December 9, 1998 1 d) What physical aspect of a planar bipolar transistor determines its Early Voltage value? e) Is it important to build a current supply source with an extremely high output resistance when biasing a common collector amplifier? Explain your answer. f) What can a circuit designer do to adjust the output voltage of the following npn bipolar diode-connected voltage source? A typical value for this voltage source is about: _____ EE105, Final, Fall 1998 Problem #1 of 4: Answer each question briefly and clearly (3 points each, total 24) 2 EE105, Final, Fall 1998 Problem #2 of 4 (26 points) 5 e) Quite frankly, this is not a very good amplifier, so go ahead and replace M1 with an npn bipolar transistor, redraw the circuit and calculate the new loaded DC voltage gain. (5 points) Problem #3 of 4 (25 points) Consider the following static CMOS logic circuit. The two capacitances on the schematic represent the capacitance of the wiring connecting these gates. For each of the following questions, make sure that you show the expressions before you plug in the specific values. A correct expression is worth 70% of the credit, even if the numerical calculation is incorrect! a) Write the logical expression for Q in terms of A, B and C, and fill out the truth table. (3 points) Q = EE105, Final, Fall 1998 Problem #2 of 4 (26 points) 6 b) Re-draw this circuit showing all the transistors that implement the logical functions depicted above in CMOS static logic, using a 5 V supply voltage. (4 points) c) All transistors have a channel length L = 2um. The widths of the n-channel transistors for the inverters and logic gates are as follows: NAND gate: Wn = 4 um, Inverter 1: Wn = 6 um, Inverter 2: Wn = 18 um, NOR gate: Wn = 4um. Determine the widths of the p-channel transistors in the circuit such that the inverters have equal propagation delays tPHL = tPLH and that the logic gates have equal worst-case propagation delays. (6 points) d) Find the numerical value of the worst-case propagation delay tp for the NAND gate. The drain-bulk capacitances can be neglected because of the large wire capacitance. (But do take into account the effect of the gate capacitance through Cox!) (6 points) EE105, Final, Fall 1998 Problem #2 of 4 (26 points) 7
