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Microelectronic Devices and Circuits Exam - UC Berkeley EE 105, Exams of Microelectronic Circuits

This is the solution for the midterm exam of the microelectronic devices and circuits course (ee 105) from the university of california, berkeley. The exam includes problems related to mos amplifiers, bjt circuits, frequency response, mos devices, and cascode amplifiers with mixed mos and bjt transistors. The solutions involve finding small-signal parameters, bias voltages, transconductance, output resistances, and voltage gains, as well as drawing circuit diagrams and bode plots.

Typology: Exams

2012/2013

Uploaded on 03/22/2013

raghav
raghav 🇮🇳

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Download Microelectronic Devices and Circuits Exam - UC Berkeley EE 105 and more Exams Microelectronic Circuits in PDF only on Docsity! UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 105: Microelectronic Devices and Circuits Spring 2008 MIDTERM EXAMINATION #2 Time allotted: 80 minutes NAME: _______SOLUTIONS________ _________________________ _________________________ (print) Last First Signature STUDENT ID#: ____________________ INSTRUCTIONS: 1. Use the values of physical constants provided below. 2. SHOW YOUR WORK. (Make your methods clear to the grader!) 3. Clearly mark (underline or box) your answers. 4. Specify the units on answers whenever appropriate. PHYSICAL CONSTANTS Description Symbol Value Electronic charge q 1.6×10-19 C Boltzmann’s constant k 8.62×10-5 eV/K Thermal voltage at 300K VT = kT/q 0.026 V Note that VT ln(10) = 0.060 V at T=300K PROPERTIES OF SILICON AT 300K Description Symbol Value Band gap energy EG 1.12 eV Intrinsic carrier concentration ni 1010 cm-3 Dielectric permittivity εSi 1.0×10-12 F/cm Electron and Hole Mobilities in Silicon at 300K SCORE: 1 / 20 25 15 20 2 / 3 / 4 / Total: / 80 Page 1 Problem 1 [20 points]: MOS Amplifiers 1) For this problem, use the following parameters for all NMOS transistors: VTH = 0.4 V, μnCox = 200 μA/V2, λ = 0.1V-1, (W/L)1 = (W/L)2 = 10. The current source is ideal. Page 2 M1 M2 VDD = 2V 100 μA inv outv bV M1 M2 VDD = 2V 100 μA inv outv bV Amplifier-A Amplifier-B a) Find the small signal parameters for M1 and M2 (gm, r0). [4pts] Since the amplifiers are biased identically and the MOSFETs are identical, the small- signal parameters for Amplifier-A will be the same as those for Amplifier-B. , , , 2 , 632 S , , , , 1 100 kΩ b) W e topology of “Amplifier-A” (i.e., common source, common base, etc)? [2pts] hat is th Cascode c) Find the voltage gain, input and output resistance of Amplifier-A. Show both the expressions and the numerical values. You can make approximations in your expression as long as they a w 10 a u p ] re ithin % cc racy. [6 ts .51 4126 ∞ 1 6.525 MΩ d) Show all parasitic capacitances of the BJTs in the circuit diagram above. Simplify the capacitances (e.g., combine all capacitances in parallel, remove capacitances that are shorted). Redraw the circuit diagram below with the simplified capacitances. [Hint: a constant DC voltage is AC ground]. [5pts] Here’s the circuit with all parasitic capacitances: And the one with the capacitances simplified: Page 5 e) Find the input and output poles of this circuits. What is the dominant pole? Find the 3-dB bandwidth of this circuit. [5pts ]. , 1 1 1 1 Page 6 2 6 10 rad/s 47.1 GHz.9 , 1 3.33 10 rad/s 5.31 GHz The dominant pole is the smaller pole, so it is 5.31 GHz . f) Construct the Bode plot of the transistor. Clearly mark the scale of both axes. The Bode plot should show both the low-frequency voltage gain as well as 3-dB bandwidth of the amplifier. [5pts] The low frequency gain on the plot is 20 log 0.975 0.22 dB. Problem 3 [15 points]: MOS Devices 3) Below is the cross section of a PMOS transistor: a) What is the doping type (n, n+, p, or p+, where “+” means high doping concentration) of [3pts] Substrate (Body) Gate S DG B i) Source: p ii) Drain: p iii) Substrate (body): n b) Which carrier(s) are involved in current conduction? (i) electrons, (ii) holes), (iii) both e ns and holes. (choose one) [3pts] lectro Holes c) If the power supply voltage is 2V and ground is 0V, what bias voltage is usually c ected to the body (substrate) of the transistor? Why? [3pts] onn 2 V We want to ensure the n-type side of the pn junctions is at the highest potential to keep them reverse biased. Otherwise, we’ll get substrate current (undesirable). d) Assume the threshold voltage of the PMOS is VTH = -0.4V. If VS = 2V, VD = 0V, find the gate voltages for which the PMOS is (i) cut-off, (ii) in between saturation and triode regions. [3pts] (i) V1.6 (ii) 0.4 V e) If a PMOS and an NMOS have exactly the same dimension (W, L, and oxide thickness), which transistor has higher mg ? Why? (Assume both are long-channel devices) [3pts] Page 7 The NMOS will have higher transconductance because electrons have higher mobility than holes and √ .
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