Electronics Circuits - Analog and Digital Electronics - Lecture Slides | EE 334, Exams of Electrical and Electronics Engineering

Download Electronics Circuits - Analog and Digital Electronics - Lecture Slides | EE 334 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! 1 EE 334 Analog Electronics Midterm Exam Review (Lectures 2-20) Diode: Why we need to understand diode? • The base emitter junction of the BJT behaves as a forward bias diode in amplifying applications. • The behavior of the diode when reverse bias is the key to the fabrication of the integrated circuits. • The diode is used in many important nonamplifer applications. eer ee en See ee Cy Se CAR ITS Se ue ++++ |\@O..- +444 ---- +++ |O@OR ++++ |(O/@| --_- The p-n Junction Depletion or space-charge region N type region Efiela ee | | prevents flowofboth | Fee ou) DOE Ulett} | cela ls Oe Cau Laue urd eee Cs ease OC emu to mcr eee st See Rin ue kod eed Cems Ce ose ttt sg eee ces DOT E TE can Ae pte cea ag c that can surmount barrier. er ead De eRe ee ees Pees eather 5 Half Wave Rectification Full-Wave Rectifiers Full-wave rectifiers cut capacitor discharge time in half and require half the filter capacitance to achieve a given ripple voltage. All specifications are the same as for half-wave rectifiers. Reversing polarity of the diodes gives a full- wave rectifier with negative output voltage. Figure 2.7 A full-wave bridge rectifier: (a) circuit showing the current direction for a positive input cycle, (b) current direction for a negative input cycle, and (c) input and output voltage waveforms Half-wave rectifier with filter Son a ast soa nda view ire a fa and fe anoyeate Filter Capacitor Relationships @ Time between peak values, T, @ Half-wave rectifier — corresponds to full period of signal (60 Hz, f = 30) ® Full-wave rectifier — one half of signal full period (60 Hz, f = 60) @ Applying the value of the RC time constant Basic Zener Voltage Regulator Rg i ANN = . — Alga , pe a te { Fei; BN Sane ounce Variable load (from filter) conditions Sizing Series Resistor R, = Se Ve thus R; = 1 @ Case 1. Ve > Vey # V,. = min, Iz = min, I, = max ° Case 2. 2. @ P, = rated diode dissipation ee Merman feemen ee ei 7 % regulation is used to measure how well the regulator is Performing its function. Voltage regulation is the measure of circuit’s ability to maintained a constant output even when input voltage or load current varies. 10 Bipolar NOR logic gate Example 3.11 Determine current and voltage in the circuit 3.43(b) Rc=1KΩ RB=20KΩ VBE(on)=0.7V VCE(sat)=0.2V β=50 Lecture #3 The process by which the quiescent output voltage is caused to fall somewhere the cutoff and saturated values is referred to as biasing. BIT Bias Stability Vin = Ringo *Vee(on) * leaRe \. Vin = Rilo +Vegion) + (B+ IpRe Teg = pW Th Vetion) 60 Rn Bt ORE * leg = BT Motion) co Rt Bt Re For Bias Stability: Ry, << (1 +B) Re For Bias Stability: Ry, << (1+ B) Re Then B (Vin = Veeion)) (B+ DRe If B>> 4, then Bi(1 +B) ~ 1 Therefore, Vin= Mee(on) Ico = Ico = [gg not a significant function of f BIT Bias Stability General Rule For Bias Stable Circuit Ryn = 0-1 (1+ 6) Re BJT Thermal Runaway ® Without Re ® Expect junction current increase to cause temperature increase (I°R) # This AT can cause further current increase thereby further increasing temperature. ® Phenomenon -- thermal runaway. ® Result -- device destruction: 12 Chapter 4 Small-Signal Modeling and Linear Amplification DC and AC Analysis • DC analysis: – Find dc equivalent circuit by replacing all capacitors by open circuits and inductors by short circuits. – Find Q-point from dc equivalent circuit by using appropriate large-signal transistor model. • AC analysis: – Find ac equivalent circuit by replacing all capacitors by short circuits, inductors by open circuits, dc voltage sources by ground connections and dc current sources by open circuits. – Replace transistor by small-signal model – Use small-signal ac equivalent to analyze ac characteristics of amplifier. – Combine end results of dc and ac analysis to yield total voltages and currents in the network. DC Equivalent for BJT Amplifier • All capacitors in original amplifier circuits are replaced by open circuits, disconnecting vI, RI, and R3 from circuit. AC Equivalent for BJT Amplifier kΩ100kΩ3.4 3 kΩ30kΩ10 21 == == RCRR RRBR •Find ac equivalent circuit by replacing all capacitors by short circuits, 15 Summary of hybrid-π-model parameters Diffusion resistance transconductance Current gain Output resistance Characteristics of a CE amplifier • It has moderately low input impedance (1K to 2K) • Its output impedance is moderately large(50K or so) • Its current gain is high • It has very high voltage gain of the order of 1500 or so • It produce very high power gain of the order of 10,000 times or 40dB • It produce phase reversal of input signal Uses: many applications because of Large gain in voltage, current and power (by voltage divider Rule) Small-Signal Analysis of Complete C-E Amplifier: AC Equivalent • Ac equivalent circuit is constructed by assuming that all capacitances have zero impedance at signal frequency and dc voltage source is ac ground. • Assume that Q- point is already known. 21 RRBR = 16 Small-Signal Analysis of Complete C-E Amplifier: Small- Signal Equivalent 3 RCRorLR = If we include an emitter resistance in the circuit, the Q-point of the circuit will be less dependant on the transistor current gain β. In order to determine the input impedance Rib, which is the resistance looking into the base of the transistor. We can write the following loop equation The overall input impedance to the amplifier is now Voltage gain is less dependant on β The voltage gain is Substantially reduced When an emitter resistor is included!! 17 How can we Improve the voltage gain ? A common collector amplifier has following chracteristics: 1 High input impedance (20-500K) 2 Low output impedance (50-2000 Ohms) 3 High current gain (50-300) 4 Voltage gain of less than 1 5 Power gain of 20 to 20dB 6 No phase reversal between input and output signals Apply KVL around the base emitter loop Using above equations we can write voltage gain as Input impedance Clearly the voltage gain is less than 1 and no phase reversal 20 • It is to be noted that the VDS measured relative to the source increases from 0 to VDS as we travel along the channel from source to drain. This is because the voltage between the gate and points along the channel decreases from VGS at the source end to VGS-VDS. • When VDS is increased to the value that reduces the voltage between the gate and channel at the drain end to Vt that is , • VGS-VDS=Vt or VDS= VGS-Vt or VDS(sat) ≥ VGS-Vt Concept of Asymmetric Channel NMOS Transistor: Saturation Region TNGSDSTNGSD VvvVv L WnKi −≥−=      for 2 ' 2 vDSAT =vGS−VTN is called the saturation or pinch-off voltage 21 Depletion-Mode MOSFETS • NMOS transistors with • Ion implantation process is used to form a built-in n-type channel in the device to connect source and drain by a resistive channel • Non-zero drain current for vGS = 0; negative vGS required to turn device off. VTN ≤0 22 Common source circuit with coupling capacitance Cc, which act an an open circuit to the dc DC equivalent circuit. Gate PMOS common source circuit If the device is biased in saturation region N-Channel MESFET Formulas (same as MOSFET) @ The transition point: Vosisay = Vos — Vin Vin = n-channel threshold voltage @ Vo5 > Vpsieat) — the saturation region: in = 2 ip = Ka(Ves — Vin) @ Vos < Vostearn — the nonsaturation region: ip = K,12(Vos - Vins - Vosl K, = n-channel conduction parameter Common JFET Configurations: DC Analysis Design Example 5.18 Objective: Des biasing eiveui aa JPET circuit with a voltage divider Consider the circuit showa in Figure 5.5%) with transistor parameters Jo; Ima, ¥ SV, and 4=0. Let Ry + Ry = 100K. Design the circuit such the the de drain current is fp = SmA snd the de drain-to-source voltige is Vps Solution: Assume the transistor is biased in the saturation region, rent is then given by n= Yoss(t Which yields Veg = -124V From Figure 5.57(b), the voltage at the source terminal is Vs = [ns ~ 5 = (50.5) - $= -25V 128-25 = -3.74V voltage as Therefore, Ry=126k2 Ry = 874k =3v Design Example 5.20 Objective: Design a MPSPT nsider the circuit shown in Figure 3.592), The LimAjv stich that Vys = 0.50V and Vyg = Solution: From Equatioa (3.36(a) the cuit with an cnhancement-mode transisior parameters are: kQ. Design the circuit sin current is aay C05 0.287 = Tawa voltage at the dean is (o.074aN0. Vv Hi 1 Ye Ks= garag™ HKe Since the gate tiva, as follows ; 2 which confirms that the transistor is biased in the saturation region, as initially assumed sis also given by Small-Signal Analysis Chapter 6  N-Channel MOSFET Small-Signal Model conte Om = 2/Ky pq (transconductance) 4 DQ Ky = n-channel conduction parameter (output resistance) 2.= channel-length modulation parameter = 2K,(Veso — Vin) \Common-Source Circuit ‘Enhancement -Mode NMOS) . ' Common-Source Circuit , (ove Small-Signal Equivalent ® A Basic Common-Source Configuration The input gate. to-source volt e is . j RY) Fa (x + 7) " Vo = —8mV gs(Toll Ro) so the small-signal voltage gain is, Example 6.3 Objective: Determine the small-signal voltage gain and input and output resistances of a coramon-source amplifier. For the cieuit shown in Figuce 6.13, the parameters ans Vp = IOV, Ry = 9K, y= WK. and Ky = SKS The tr Kk nA/W and 4 = 0.01V". Assume Solution: DC Cakulations: The de or quiescent gate-to-source volt tow ( The quiescent drain current is sistor parameters are: Vzy = 1.3, 21 Jaw =291V Ing = KaWaso — Viv = (0.52.91 ~ LSP = LA, and the quiescent driinsto-source voltage is Vosy = Vow ~ log Ry = 10 ~ (INS) = SV Since Vpsq * Vaso ~ Vnys the transistor is biased in the saturation region ‘Small-signal Voltage Gain: The small-signal transconductance fu i ther Kn = 2K (Vaso ~ Vry) = 0.5)291 ~ 1.8) = LAL A/V and the smal nal output resi falpol! = (ony = 10K The amplifier input resistance is Ry = RyRy = 10.9)29.1 = 20.642 From Figur 14 and Equation (6.29), the smallsignal voltage gain is Input and Output Resistances: ) = -c.anc10045) Re Rs (ratty (a8 s) Ry = RyRy = 70.9129.1 = 20.642 2 Ry = Rots = Si100 = 4.76k2 27 The trend of the voltage gain of the source follower is identical that of bipolar emitter follower :NMOS source follower ⇒ Which is output impedance 30 Transformer coupled class A amplifier (improved version) : (emitter follower) 31 (cont.) It has high efficiency, It is primarily due to the fact that there is no power drawn by circuit under zero signal conditions. Since in push pull arrangement 180 phase difference exist between even-order harmonics produced by each transistor, they cancel out thereby giving an almost distortion free output. This automatics cancellation of all even order harmonics from the output current makes class push pull amplifier highly desirable for communication sound equipments. Uses: Class B push pull amplifier are extensively used for audio work in portable recorder players, as stereo amplifiers, and in radio receiver. It, in fact means locating the Q-point of each transistor slightly above the cutoff. So that each one operate more than one half cycle. Advantage and disadvantage of class AB amplifier Since, for a zero input signal, quiescent collector currents exist in the out- put transistors, the average power supplied by each source and the average power dissipated in each transistor are larger than for a class-B configuration, This means that the power conversion efficiency for a class-AB output stage is| less than that for an idealized class-B circuit. In addition, the required power handling capability of the transistors in a class-AB circuit must be slightly larger than in a class-B circuit. However, since the quiescent collector currents Jeg are usually small compared to the peak current, this increase in power dissipation is not great. The advantage of eliminating crossover distortion in| the class-AB output stage greatly outweighs the slight disadvantage of reduced conversion efficiency and increased power diss: on. in a MOSFET class-AB Example 8.7 objective: Determine the required biasing output st re 8.25. The parameters are Vpp = 10V and Ry = 202. The transistors are matched, and the parameters are K =0.20A/V? and Vp] =1V. The quiewent drain current is to be 20 percent of the load current when vo =5V Solution: For ve — SV. Then, for Ig = 0.05 A when vg = 0, we have Vo Ing = 0.05 = K (22 — 5 rl) =(0 20) (22 - 1 which yields Vgg/2 = 1.50V for vg positive is 0.25 A, we have =212¥ TI le voltage of My is sop = Van — Voss =3-2.12=0.88¥ whick means that Af, is cut off aud fy = 4. Finally, the input voltage is y=5 4212-13 =562V Comment: Since vy expected. gain of this output stage is less than unity, as Class-AB Output Stage with Diode Biasing In a class-AB circuit, the Vgg voltage that provides the quiescent bias for the loutput transistors can be established by voltage drops across diodes, as shown in Figure 8.30. A constant current Jp, is used to establish the sequised voltage lacross the pair of diodes, or the diode-connected transistors, D, and D). Since ID, and Dy are not ni ssarily matched with Q, and Q, 0 ),, the qniescent transistor currents may not be equal 10 pins: