Download Understanding VHDL: The Industry Standard Language for Digital Design and more Lecture notes Embedded Systems in PDF only on Docsity! Why VHDL? Shorter development time for electronic design Simpler maintenance Traditional: schematic design 1 VHDL Background VHDL - VHSIC Hardware Description Language. Industry Standard Language. ‘70s and ‘80s by U.S Department of Defense. Sophisticated electronics components. Standardized by the IEEE in 1987. 2 VHDL Concepts Architecture Bodies Hardware abstraction of a digital system Design Entity Entity A1 A2 A3 5 VHDL Program file structure Entity Declaration Architecture Body Package declaration Package body Configuration declaration 6 Libraries in VHDL library IEEE; use IEEE.std_logic_1164.all; http:// www.csee.umbc.edu/portal/help/VHDL/packages/std_logic_11 64.vhd Logical operators like and, or , xor etc… Conversion functions like To_bit, To_bitvector etc… 7 Libraries in VHDL use IEEE.math_real.all; http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd Functions like SQRT, EXP, LOG, LOG10, SIN, COS, TAN, SINH, COSH, ARCSIN, ARCCOS, ARCTAN, TANH, ARCSINH, ARCCOSH, ARCTANH etc… use IEEE.math_complex.all; http://www.csee.umbc.edu/portal/help/VHDL/packages/mathpack.vhd Functions like COMPLEX_TO_POLAR, POLAR_TO_COMPLEX, ABS, SQRT, EXP, LOG, SIN, COS, TAN, SINH, COSH, TANH, +,-,*,/ etc… 10 Entity Declaration Syntax entity NAME_OF_ENTITY is port (signal_names: mode type; signal_names: mode type; : signal_names: mode type); end [NAME_OF_ENTITY] ; NAME_OF_ENTITY: user defined Signal_names: list of signals (both input and output) Mode: in, out, buffer, inout type: boolean, integer, character, std_logic 11 Architecture Declaration Syntax architecture architecture_name of NAME_OF_ENTITY is -- Declarations begin -- VHDL Statements End architecture_name; Internal details of Architecture can be modeled in 4 different styles: i. Behavioral - sequential assignment statements. ii. Dataflow – concurrent assignments. iii. Structural - set of interconnected components iv. Mixed Mode 12 Package Package Package declaration Package body Package declaration may contain Basic declarationsSignal declarations Attribute declarationsComponent declarations Types, subtypes Constants SubprogramsUse clause 15
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Elaboration Phase Hierarchy of entity is expanded and Linked. Components are bound to the entities in library. Top –level entity is built as network of behavioral models. Storage is allocated for all data objects(signals, variables and co constants) declared in design. Initial values are assigned. Initialization Phase Effective values for explicitly declared signals are computed. Processes are executed once until they suspend. Simulation time is reset to 0 ns. Simulation Process 17 Identifier Sequence of 1 or more characters. A legal character is an upper case or lower case or a digit or underscore. 1st character must be a letter and the last character may not be underscore. Lower-case and Upper-case letters are identical when used in an identifier. E.g., Count, COUNT, CounT. Two underscore characters cannot appear consecutively. VHDL Language Elements 20 Key Words or Reserved Words abs, all, assert, begin, bus, case, access, and, attribute, after, architecture, alias, array, block, body, buffer, case, component, configuration, constant, disconnect, downto, else, exit, elsif, end, entity, file, for, function, generate, generic, guarded, if, in , inout, is , label, library, linkage, loop, map, mod, nand, new, next, nor, not, null, of, on, open, or, others, out, package, port, procedure, process, range, record, register, rem, report, return, select, severity, signal, subtype, then, to, transport, type, units, until, use, variable, wait, when, while, with, xor. VHDL Language Elements 21 Data Types 22 Data Types Types Access Composite Array RecordScalar Integer Real Enumerated Physical
