Microprogramming and Memory Systems: Arithmetic Micro-operations and Memory Hierarchy, Lecture notes of Computer Architecture and Organization

Download Microprogramming and Memory Systems: Arithmetic Micro-operations and Memory Hierarchy and more Lecture notes Computer Architecture and Organization in PDF only on Docsity! 1 | P a g e b i i z a y @ g m a i l . c o m Unit 1 – Data Representation Data Types In computer science, a data type or simply type is a classification identifying one of various types of data, such as real, integer or Boolean, that determines the possible values for that type; the operations that can be done on values of that type; the meaning of the data; and the way values of that type can be stored. Data types are used within type systems, which offer various ways of defining, implementing and using them. Common data types may include:  Integers  Booleans  Characters  Floating-point numbers  Alphanumeric strings The computer registers contain either data or control information. Data are numbers and other binary-coded information that are operated on. Control information is a bit or group of bits used to specify the sequence of command signals needed for data manipulation. Possible data types in registers:  Numbers used in computations  Letters of the alphabet used in data processing  Other discrete symbols used for specific purposes Data Representation 5 Hrs. Data Representation 1.5 Hrs. Data Types Number Systems Alphanumeric Representation Complements (r’s and r-1’s) Fixed point Representation 1 Hr. Integer Representation Arithmetic Addition, Subtraction, and Overflows Decimal Fixed point Representation Floating point Representation 1 Hr. Binary and Decimal Codes 1 Hr. Gray, BCD, ASCII, Excess-3 Codes Error Detection Code 0.5 Hr. Parity bit, Parity checker and Parity generator Downloaded from CSIT Tutor 2 | P a g e b i i z a y @ g m a i l . c o m All types of data, except binary numbers, are represented in binary-coded form. Numbers are represented by a string of digit symbols. Based on number systems two basic data types are implemented in the computer system: fixed point numbers and floating point numbers. Representing numbers in such data types is commonly known as fixed point representation and floating point representation. Number System Number systems are used to describe the quantity of something or represent certain information. Number of digits used in a number system is called its base or radix (r). We can categorize number system as below: Binary number system (r = 2) Binary number system was introduced by an Indian- scholar Pingala in around 5th -2nd centuries in BC. Long and short syllables were used by him to illustrate the two types of numbers, it is more like Morse code. Gottfried Leibniz in 1679 introduced the modern type of binary number system which we still use. The number system with only two digit 0 and 1 is known as binary number system. Here, zero is represented by a symbol '0' and one is represented as '1'. Binary is another way of saying base-2. Binary number system has the base (or radix) 2 and the numbers in this system are formed with two digits 1 & 0. Figure: Representing binary number 1001101 EXAMPLE: Binary Number: (10101)2 Calculating Decimal Equivalent: Downloaded from CSIT Tutor 5 | P a g e b i i z a y @ g m a i l . c o m = (1x1000) + (2x100) + (3x10) + (4x1) = (1x103) + (2x102) + (3x101) + (4x100) = 1000 + 200 + 30 + 1 = (1234)10 Number System Conversion Decimal to Other Base System Steps: Step 1 - Divide the decimal number to be converted by the value of the new base. Step 2 - Get the remainder from Step 1 as the rightmost digit (least significant digit) of new base number. Step 3 - Divide the quotient of the previous divide by the new base. Step 4 - Record the remainder from Step 3 as the next digit (to the left) of the new base number. Repeat Steps 3 and 4, getting remainders from right to left, until the quotient becomes zero in Step 3. The last remainder thus obtained will be the most significant digit (MSD) of the new base number. Example: Decimal Number: (29)10 Calculating Binary Equivalent: As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse order so that the first remainder becomes the least significant digit (LSD) and the last remainder becomes the most significant digit (MSD). Decimal Number: (29)10 = Binary Number: (11101)2 Downloaded from CSIT Tutor 6 | P a g e b i i z a y @ g m a i l . c o m Example: Conversion of Decimal (41.6875)10 to Binary Other base system to Decimal System Steps: Step 1 - Determine the column (positional) value of each digit (this depends on the position of the digit and the base of the number system). Step 2 - Multiply the obtained column values (in Step 1) by the digits in the corresponding columns. Step 3 - Sum the products calculated in Step 2. The total is the equivalent value in decimal. Example: Binary Number: (11101)2 Calculating Decimal Equivalent: Binary Number: (11101)2 = Decimal Number: (29)10 Other Base System to Non-Decimal System Steps: Step 1 - Convert the original number to a decimal number (base 10). Step 2 - Convert the decimal number so obtained to the new base number. Example: Octal Number: (25)8 Downloaded from CSIT Tutor 7 | P a g e b i i z a y @ g m a i l . c o m Calculating Binary Equivalent: STEP 1: CONVERT TO DECIMAL Octal Number: (25)8 = Decimal Number: (21)10 STEP 2: CONVERT DECIMAL TO BINARY Decimal Number: (21)10 = Binary Number: (10101)2 Octal Number: (25)8 = Binary Number: (10101)2 Shortcut method - Binary to Octal Steps: Step 1 - Divide the binary digits into groups of three (starting from the right). Step 2 - Convert each group of three binary digits to one octal digit. Example: Binary Number: (10101)2 Calculating Octal Equivalent: Binary Number: (10101)2 = Octal Number: (25)8 Downloaded from CSIT Tutor 10 | P a g e b i i z a y @ g m a i l . c o m Example 1: Using 2’s complement, subtract 1010100 – 1000011 X – Y X = 1010100 2’s complement of Y = + 0111101 Sum = 10010001 Discard end carry 27 = - 10000000 Answer: X - Y = 0010001 Example 2: Using 2’s complement, subtract 1000011 – 1010100 Y – X Y = 1000011 2’s complement of X = +0101100 Sum = 1101111 No end carry Answer: Y – X - (2’s complement of 1101111) = -0010001 10’s complement We have to add 1 with the 9’s complement of any number to obtain the desired 10's complement of that number. Or, if we want to find out the 10's complement directly, we can do it by following the following formula, (10n - number), where n = number of digits in the number. An example is given below to illustrate the concept of obtaining 10’s complement. Example: The 10’s complement of 546700 is 1000000 – 546700 = 453300 The 10’s complement of 12389 is 100000 - 12389 = 87611 Downloaded from CSIT Tutor 11 | P a g e b i i z a y @ g m a i l . c o m Other Examples: The 10’s complement of decimal 2389 = (104 –1) – 2389 + 1 = 7611. The 10’s complement of decimal 012389 = (106 –1) – 012389 + 1 = 987602 The 10’s complement of decimal 246700 = (106 –1) – 246700 + 1 = 753300 Example 1: Using 10’s complement, subtract 72532 – 3250 M – N M = 72532 10’s complement of N = +96750 (99999 – 03250) + 1 Sum = 169282 Discard end carry 105 = -100000 Answer: = 69282 Example 2: Using 10’s complement, subtract 3250 – 72532 M – N M = 03250 10’s complement of N = +27468 (99999 – 72532) + 1 Sum = 30718 No end carry Answer: - (10’s complement of 30718) = - 69282 (R-1)'s Complement The diminished radix complement is referred to as the (r-1)'s complement. (R-1)'s complement of a number N is defined as (rn -1) – N. Where, N is the given number r is the base of number system n is the number of digits in the given number To get the (R-1)'s complement fast, subtract each digit of a number from (R-1) Example:  9's complement  1's complement 1's complement The 1's complement of a number is found by changing all 1's to 0's and all 0's to 1's. This is called as taking complement or 1's complement. Example of 1's Complement is as follows: Downloaded from CSIT Tutor 12 | P a g e b i i z a y @ g m a i l . c o m Other Examples: The 1’s complement of 1011000 is 0100111 The 1’s complement of 0101101 is 1010010 Example 1: Using 1’s complement, subtract X – Y = 1010100 – 1000011 X = 1010100 1’s complement of Y = + 0111100 (+1 End-around carry) Sum = 10010000 + 1 Answer: X - Y = 0010001 Example 2: Using 1’s complement, subtract Y – X 1000011 – 1010100 Y = 1000011 1’s complement of X = + 0101011 Sum = 1101110 No end carry Answer: Y – X - (1’s complement of 1101110) = -0010001 9’s complement To obtain the 9’s complement of any number we have to subtract the number with (10n - 1) where n = number of digits in the number, or in a simpler manner we have to divide each digit of the given decimal number with 9. Example: The 9’s complement of 546700 is 999999 - 546700= 453299 Downloaded from CSIT Tutor 15 | P a g e b i i z a y @ g m a i l . c o m Disadvantages  Negative numbers cannot be represented.  The need of different notation to represent negative numbers. In all the above three schemes, the most-significant bit (MSB) is called the sign bit. The sign bit is used to represent the sign of the integer - with 0 for positive integers and 1 for negative integers. The magnitude of the integer, however, is interpreted differently in different schemes. Sign-Magnitude Representation  sign bit is 0 for positive, 1 for negative  magnitude part = absolute value of number  2 representations for 0. (0000 and 1000) Example 1: Suppose that n=8 and the binary representation is (0 100 0001)2. Sign bit is 0 ⇒ positive Absolute value is (100 0001)2 = (65)10 Hence, the integer is +(65)10 Example 2: Suppose that n=8 and the binary representation is (1 000 0001)2. Sign bit is 1 ⇒ negative Absolute value is (000 0001)2 = (1)10 Hence, the integer is –(1)10 Example 3: Suppose that n=8 and the binary representation is (0 000 0000)2. Sign bit is 0 ⇒ positive Absolute value is (000 0000)2 = (0)10 Hence, the integer is +(0)10 Downloaded from CSIT Tutor 16 | P a g e b i i z a y @ g m a i l . c o m Example 4: Suppose that n=8 and the binary representation is (1 000 0000)2. Sign bit is 1 ⇒ negative Absolute value is (000 0000)2 = (0)10 Hence, the integer is –(0)10 The drawbacks of sign-magnitude representation are:  Addition and subtractions are difficult.  Signs and magnitude, both have to carry out the required operation.  There are two representations and for the number zero, which could lead to inefficiency and confusion. (0000 0000)2 = +010 (1000 0000)2 = -010  Positive and negative integers need to be processed separately. 1’s complement Representation  sign bit (MSB) is 1 for negative, 0 for positive  negation is complement, e.g. 5 = 0101, -5 = 1010  two representations for 0: 1111 and 0000 Example 1: Suppose that n=8 and the binary representation (0 100 0001)2. Sign bit is 0 ⇒ positive Absolute value is (100 0001)2 = (65)10 Hence, the integer is +(65)10 Example 2: Suppose that n=8 and the binary representation (1 000 0001)2. Sign bit is 1 ⇒ negative Absolute value is the complement of (000 0001)2, i.e., (111 1110)2 = (126)10 Hence, the integer is –(126)10 Downloaded from CSIT Tutor 17 | P a g e b i i z a y @ g m a i l . c o m Example 3: Suppose that n=8 and the binary representation (0 000 0000)2. Sign bit is 0 ⇒ positive Absolute value is (000 0000)2 = (0)10 Hence, the integer is +(0)10 Example 4: Suppose that n=8 and the binary representation (1 111 1111)2. Sign bit is 1 ⇒ negative Absolute value is the complement of (111 1111)2, i.e., (000 0000)2 = (0)10 Hence, the integer is -(0)10 Again, the drawbacks are:  There are two representations for zero. (0000 0000)2 = +010 (1111 1111)2 = -010  The positive integers and negative integers need to be processed separately. 2’s complement Representation  sign bit (MSB) is 1 for negative, 0 for positive  add 1 to 2's complement negative numbers  only one representation for 0  negation is complement + 1, e.g. 5 = 0101, -5 = 1010 + 1 = 1011 Example 1: Suppose that n=8 and the binary representation (0 100 0001)2. Sign bit is 0 ⇒ positive Absolute value is (100 0001)2 = (65)10 Hence, the integer is +(65)10 Example 2: Suppose that n=8 and the binary representation (1 000 0001)2. Sign bit is 1 ⇒ negative Absolute value is the complement of (000 0001)2 plus 1, i.e., (111 1110)2 + (1)2 = (127)10 Hence, the integer is -(127)10 Example 3: Suppose that n=8 and the binary representation (0 000 0000)2. Sign bit is 0 ⇒ positive Absolute value is (000 0000)2 = (0)10 Hence, the integer is +(0)10 Example 4: Suppose that n=8 and the binary representation (1 111 1111)2. Sign bit is 1 ⇒ negative Absolute value is the complement of (111 1111)2 plus 1, i.e., (000 0000)2 + (1)2 = (1)10 Hence, the integer is -(1)10 Downloaded from CSIT Tutor 20 | P a g e b i i z a y @ g m a i l . c o m -13 → 11110011 (2's complement form) Subtraction is changed to addition by taking 2's complement of the subtrahend (-13) to give (+13). -6 → 11111010 +13 → 00001101 +7 → 100000111 (discarding end carry). Overflow When two numbers of n digits are added and the sum occupies n+1 digits, we say that an overflow has occurred. A result that contains n+1 bits can't be accommodated in a resister with a standard length of n-bits. For this reason many computers detect the occurrence of an overflow setting corresponding flip-flop. An overflow may occur if two numbers added are both positive or both negative. Example: Two signed binary numbers +70 and +80 are stored in two 8-bit resisters. Since the sum of numbers 150 exceeds the capacity of the resister (since 8-bit resister can store values ranging from +127 to -128), hence the overflow. Overflow Detection An overflow condition can be detected by observing two carries: carry into the sign bit position and carry out of the sign bit position. Consider example of above 8-bit resister, if we take the carry out of the sign bit position as a sign bit of the result, 9-bit answer so obtained will be correct. Since answer cannot be accommodated within 8-bits, we say that an overflow occurred. If these two carries are equal ==> no overflow If these two carries are not same ==> overflow condition is produced. If two carries are applied to an exclusive-OR gate, an overflow will be detected when output of the gate is equal to 1. Decimal Fixed-Point Representation Decimal number representation = f (binary code used to represent each decimal digit). Output of this function is called the Binary coded Decimal (BCD). A 4-bit decimal code requires 4 flip-flops for each decimal digit. Example: 4385 = (0100 0011 1000 0101)BCD Disadvantages of BCD representation: Downloaded from CSIT Tutor 21 | P a g e b i i z a y @ g m a i l . c o m  wastage of memory  Circuits for decimal arithmetic are quite complex. Advantages of BCD representation:  Eliminate the need for conversion to binary and back to decimal. (since applications like Business data processing requires less computation than I/O of decimal data, hence electronic calculators perform arithmetic operations directly with the decimal data (in binary code)) For the representation of signed decimal numbers in BCD, sign is also represented with 4-bits, plus with 4 0's and minus with 1001 (BCD equivalent of 9). Negative numbers are in 10's complement form. Consider the Addition: (+375) + (-240) = +135 [0→positive, 9→negative in case of radix 10] To obtain the 10’s complement of a BCD number, first take the 9’s complement and then add one to the least significant digit. Limitation of Fixed-Point Representation To represent large numbers or very small numbers we need a very long sequences of bits. This is because we have to give bits to both the integer part and the fraction part. Floating Point Representation A floating-point number (or real number) can represent a very large (1.23×1088) or a very small (1.23×10-88) value. It could also represent very large negative number (-1.23×1088) and very small negative number (-1.23×1088), as well as zero, as illustrated: In the decimal system there are 2 ways of floating point representation: Scientific Notation and Floating point notation. A floating-point number is typically expressed in the scientific notation, with a fraction (F), and an exponent (E) of a certain radix (r), in the form of F × rE. Decimal numbers use radix of 10 (F × 10E); while binary numbers use radix of 2 (F × 2E). Downloaded from CSIT Tutor 22 | P a g e b i i z a y @ g m a i l . c o m Representation of floating point number is not unique. For example, the number 55.66 can be represented as 5.566×101, 0.5566×102, 0.05566×103, and so on. The fractional part can be normalized. In the normalized form, there is only a single non-zero digit before the radix point. For example, decimal number 123.4567 can be normalized as 1.234567×102; binary number (1010.1011)2 can be normalized as (1.011011)2×23. Example: Scientific notation Floating point notation 1,245,000,000,000 = 1.245×1012 0.1245×1013 0.00001245 = 1.245×10-5 0.1245×10-4 -0.00001245 = -1.245×10-5 -0.1245×10-4 Thus, there are three parts in the floating-point representation: a. The sign bit (S) is self-explanatory (0 for positive numbers and 1 for negative numbers). b. For the exponent (E), a so-called bias (or excess) is applied so as to represent both positive and negative exponent. The bias is set at half of the range. For single precision with an 8-bit exponent, the bias is 127 (or excess-127). For double precision with a 11-bit exponent, the bias is 1023 (or excess-1023). c. The fraction (F) (also called the mantissa or significand) is composed of an implicit leading bit (before the radix point) and the fractional bits (after the radix point). The leading bit for normalized numbers is 1; while the leading bit for denormalized numbers is 0. Suppose we use 16 bit words Downloaded from CSIT Tutor 25 | P a g e b i i z a y @ g m a i l . c o m 2. Non-Weighted Codes: Each bit has no positional value 1. Excess-3 code 2. Gray code 3. Five bit BCD 3. Self-Complementing codes or Reflective codes Code for one digit will be the complement of other 1. 2421 2. 5211 3. Excess-3 4. Sequential Codes Succeeding number is one more than the previous one 1. 8421 2. Excess-3 5. Alphanumeric codes 1. American Standard Code for Information Interchange (ASCII) 2. Extended Binary Coded Decimal Interchange Code (EBCDIC) 3. Hollerith Code 4. Five bit Baudot Code 5. Morse Code 6. Error Detection and Correction Codes For reliable transmission and storage of digital data, error detection and correction is required. Examples of codes which permit error detection and error correction are: Parity Codes, Hamming Code, etc. Gray Code: It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights assigned to the bit position. It has a very special feature that has only one bit will change, each time the decimal number is incremented as shown in fig. As only one bit changes at a time, the gray code is called as a unit distance code. The gray code is a cyclic code. Gray code cannot be used for arithmetic operation. Downloaded from CSIT Tutor 26 | P a g e b i i z a y @ g m a i l . c o m The Gray code consists of sixteen 4-bit code words to represent the decimal Numbers 0 to 15. For Gray code, successive code words differ by only one bit from one to the next as shown in the table above and further illustrated in the Figure below. Application of Gray Code  Gray code is popularly used in the shaft position encoders.  A shaft position encoder produces a code word which represents the angular position of the shaft. BCD Code: One commonly used code is the Binary Coded Decimal (BCD) also known as packet decimal code which corresponds to the first 10 binary representations of the decimal digits 0-9. The BCD code requires 4 bits to represent the 10 decimal digits. In the BCD, with four bits we can represent sixteen numbers (0000 to 1111). But in BCD code only first ten of these are used (0000 to 1001). A total of 6 combinations will be unused. The position weights of the BCD code are 8, 4, 2, 1. Group of 4 binary bits is a nibble. A nibble representing a number greater than 9 is invalid BCD. The remaining six code combinations i.e. 1010 to 1111 are invalid in BCD. Below is a list of the decimal numbers 0 through 9 and the binary conversion. Downloaded from CSIT Tutor 27 | P a g e b i i z a y @ g m a i l . c o m The 8421 BCD code for 9.2 is 1001.0010. BCD for 9.2 The 4221 BCD code for 9.2 is 1111.0010. The 5421 BCD code for 9.2 is 1100.0010. Note: The numbers 4, 2, 2, 1 in 4221 BCD and 5, 4, 2 and 1 in 5421 BCD represent weights of the relevant bits. Advantages of BCD Codes  It is very similar to decimal system.  We need to remember binary equivalent of decimal numbers 0 to 9 only, such as those found in digital clocks or digital voltmeters. Disadvantages of BCD Codes  The addition and subtraction of BCD have different rules.  The BCD arithmetic is little more complicated.  BCD needs more number of bits than binary to represent the decimal number. So BCD is less efficient than binary. ASCII Code: The American Standard-Code for Information Interchange (ASCII) pronounced "as-kee" is a 7-bit code based on the ordering of the English alphabets. The ASCII codes are used to represent alphanumeric data in computer input/output. It represents a total of 128 characters. These include 95 printable characters including 26 upper-case letters (A to Z), 26 lowercase letters (a to z), 10 numerals (0 to 9) and 33 special characters such as mathematical symbols, space character etc. It also defines codes for 33 non-printing obsolete characters except for carriage return and/or line feed. The below table lists the 7 bit ASCII code containing the 95 printable characters. The format of ASCII code for each character is X6X5X4X3X2X1X0 where each X is 0 or 1. For instance, letter D is coded as 1000100. More examples are: The ASCll-7 code for ‘d’ is 1100100 as seen from the table. The ASCll-7 code for '+' is 0101011 as seen from the table. An eight-bit version of the ASCII code, known as US ASCII-8 or ASCII-8, has also been developed. Since it uses 8-bits, so this version of ASCII can represent a maximum of 256 characters. Downloaded from CSIT Tutor 30 | P a g e b i i z a y @ g m a i l . c o m Advantages of Binary Code Following is the list of advantages that binary code offers.  Binary codes are suitable for the computer applications.  Binary codes are suitable for the digital communications.  Binary codes make the analysis and designing of digital circuits if we use the binary codes.  Since only 0 & 1 are being used, implementation becomes easy. Binary to BCD Conversion Steps: Step 1 -- Convert the binary number to decimal. Step 2 -- Convert decimal number to BCD. Example: convert (11101)2 to BCD. Step 1 - Convert to Decimal Binary Number: (11101)2 Calculating Decimal Equivalent: Binary Number: (11101)2 = Decimal Number: (29)10 Downloaded from CSIT Tutor 31 | P a g e b i i z a y @ g m a i l . c o m Step 2 - Convert to BCD Decimal Number: (29)10 Calculating BCD Equivalent. Convert each digit into groups of four binary digits equivalent. Result BCD to Binary Conversion Steps Step 1 -- Convert the BCD number to decimal. Step 2 -- Convert decimal to binary. Example: convert (00101001)BCD to Binary. STEP 1 - CONVERT TO BCD BCD Number: (00101001)BCD Calculating Decimal Equivalent. Convert each four digit into a group and get decimal equivalent or each group. BCD Number: (00101001)BCD = Decimal Number: (29)10 STEP 2 - CONVERT TO BINARY Used long division method for decimal to binary conversion. Decimal Number: (29)10 Calculating Binary Equivalent: Downloaded from CSIT Tutor 32 | P a g e b i i z a y @ g m a i l . c o m As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse order so that the first remainder becomes the least significant digit (LSD) and the last remainder becomes the most significant digit (MSD). Decimal Number: (29)10 = Binary Number: (11101)2 Result BCD to Excess-3 Steps Step 1 -- Convert BCD to decimal. Step 2 -- Add (3)10 to this decimal number. Step 3 -- Convert into binary to get excess-3 code. Example: convert (1001)BCD to Excess-3. STEP 1 - CONVERT TO DECIMAL (1001)BCD = (9)3 STEP 2 - ADD 3 TO DECIMAL (9)10 + (3)10 = (12)10 STEP 3 - CONVERT TO EXCESS-3 (12)10 = (1100)2 Result Excess-3 to BCD Conversion Steps Downloaded from CSIT Tutor 35 | P a g e b i i z a y @ g m a i l . c o m At the receiver end, an error is detected if the message does not match have the proper parity (odd/even). Parity bits can detect the occurrence 1, 3, 5 or any odd number of errors in the transmitted message. No error is detectable if the transmitted message has 2 bits in error since the total number of 1’s will remain even (or odd) as in the original message. In general, a transmitted message with even number of errors cannot be detected by the parity bit. Binary information may be transmitted through some communication medium, e.g. using wires or wireless media. Noise in the transmission medium may cause the transmitted binary message to be corrupted by changing a bit from 0 to 1 or vice versa. To be able to detect errors at the receiver end, the sender sends an extra bit (parity bit). How does error detection take place? The parity checking at the receiver can detect the presence of an error if the parity of the receiver signal is different from the expect parity. That means if is known that the parity of the transmitted signal is always going to be "even" and if the received signal has an odd parity then the receiver can conclude that the received signal is not correct. If presence of error is detected then the receiver will ignore the received byte and request for retransmission of the same byte to the transmitter. Parity Generator Parity generator and checker networks are logic circuits constructed with exclusive-OR functions. Consider a 3-bit message to be transmitted with an odd parity bit. At the sending end, the odd parity is generated by a parity generator circuit. The output of the parity checker would be 1 when an error occurs i.e. no. of 1’s in the four inputs is even. P = x⊕y⊕z Message (xyz) Parity bit (odd) 000 1 001 0 010 0 011 1 100 0 101 1 110 1 111 0 Downloaded from CSIT Tutor 36 | P a g e b i i z a y @ g m a i l . c o m Parity Checker Considers original message as well as parity bit e = p⊕x⊕y⊕z e= 1 => No. of 1’s in pxyz is even => Error in data e= 0 => No. of 1’s in pxyz is odd => Data is error free Circuit diagram for parity generator and parity checker is shown below. At the sending end, the message is applied to a parity generator. The message, including the parity bit, is transmitted. At the receiving end, all the incoming bits are applied to a parity checker. Any odd number of errors are detected. Figure: Error detection with odd parity bit Parity generators and checkers are constructed with XOR gates (odd function). An odd function generates 1 if an odd number of input variables are 1. Book References: (1) Andrew S. Tanenbaum, “Structured Computer Organization”, Fourth Edition. (2) M. Morris Mano, “Computer System Architecture”, Pearson, 3rd Ed, 2004. (3) M. Morris Mano, “Logic and Computer Design Fundamentals”, Pearson Education, 2nd Edition (4) John P. Hayes, “Computer Architecture & Organization”. (5) William Stalling, “Computer Organization & Architecture”. Downloaded from CSIT Tutor 37 | P a g e b i i z a y @ g m a i l . c o m Web References: (6) http://en.wikipedia.org (7) http://www.eda.kent.ac.uk/ (8) http://ecomputernotes.com/ (9) http://www.tutorialspoint.com/ Assignments: (1) Why do 0 through 9 have ASCII values? (2) (37)10 has 0010 0101 in signed magnitude notation. Find the signed magnitude of – (37)10? (3) Using the signed magnitude notation find the 8-bit binary representation of the decimal value (24)10 and – (24)10. (4) Find the signed magnitude of – (63)10 using 8-bit binary sequence? (5) Determine the decimal value represented by 10001011 in each of the following three systems.  Unsigned notation?  Signed magnitude notation?  Two’s complements? (6) Use the ASCII table to write the ASCII code for the following:  CIS110  6 = 2*3 (7) Derive the circuit for a 3-bit parity generator and a 4-bit parity checker using even parity bit. (8) Differentiate between parity checker and parity generator. (T.U. 2066) (9) Explain the error detection code with example. (T.U. 2068) (10) Explain the subtraction algorithm with signed 2’s compliment. (T.U. 2067) (11) What is an error detection code? Explain with example. (T.U. 2070) (12) Differentiate between fixed point representation and floating point representation. (T.U. 2069) (13) Write short notes on:  Alphanumeric Representation  Parity Generator (T.U. 2069) A Gentle Advice: Please go through your text books and reference books for detail study!!! Thank you all. Notes Compiled By: Bijay Mishra biizay.blogspot.com 9813911076 or 9841695609 Downloaded from CSIT Tutor 3 | P a g e b i i z a y @ g m a i l . c o m The additional arithmetic micro-operations are  Add with carry  Subtract with borrow  Transfer/Load Summary of Typical Arithmetic Micro-Operations: R3 ← R1 + R2 R3 ← R1 - R2 R2 ← R2’ R2 ← R2’+ 1 R3 ← R1 + R2’+ 1 R1 ← R1 + 1 R1 ← R1 - 1 Contents of R1 plus R2 transferred to R3 Contents of R1 minus R2 transferred to R3 Complement the contents of R2 (1’s Complement) 2's complement the contents of R2 (Negate) R1 plus 2's complement the contents of R2 (Subtraction) Increment the content of R1 by 1 Decrement the content of R1 by 1 Binary Adder Figure: 4-bit binary adder To implement the add micro-operation with hardware, we need the resisters that hold the data and the digital component that performs the arithmetic addition. The digital circuit that generates the arithmetic sum of two binary numbers of any lengths is called Binary Adder. The binary adder is constructed with the full-adder circuit connected in cascade, with the output carry from one full-adder connected to the input carry of the next full-adder. An n-bit binary adder requires n full-adders. The output carry from each full-adder is connected to the input carry of the next-high-order-full-adder. Inputs A and B come from two registers R1 and R2. The subtraction A-B can be carried out by the following steps  Take the 1’s complement of B (invert each bit)  Get the 2’s complement by adding 1  Add the result to A FA B0 A0 S0 C0FA B1 A1 S1 C1FA B2 A2 S2 C2FA B3 A3 S3 C3 C4 Downloaded from CSIT Tutor 4 | P a g e b i i z a y @ g m a i l . c o m Binary Adder-Subtractor Figure: 4-bit adder-subtractor The addition and subtraction operations can be combined into one common circuit by including an exclusive-OR gate with each full-adder. The mode input M controls the operation the operation. When M=0, the circuit is an adder and when M=1 the circuit becomes a subtractor. Each exclusive-OR gate receives input M and one of the inputs of B. 1. When M=0: B ⊕ M = B ⊕ 0 = B, i.e. full-adders receive the values of B, input carry is B and circuit performs A+B. 2. When M=1: B ⊕ M = B ⊕ 1 = B' and C0= 1, i.e. B inputs are all complemented and 1 is added through the input carry. The circuit performs A + (2's complement of B). Binary Incrementer Figure: 4-bit binary Incrementer The increment micro-operation adds one to a number in a register. For example, if a 4-bit register has a binary value 0110, it will go to 0111 after it is incremented. Increment micro-operation can be done with a combinational circuit (half-adders connected in cascade) independent of a particular register. FA B0 A0 S0 C0C1FA B1 A1 S1 C2FA B2 A2 S2 C3FA B3 A3 S3C4 M HA x y C S A0 1 S0 HA x y C S A1 S1 HA x y C S A2 S2 HA x y C S A3 S3C4 Downloaded from CSIT Tutor 5 | P a g e b i i z a y @ g m a i l . c o m Arithmetic Circuit The arithmetic micro-operations can be implemented in one composite arithmetic circuit. By controlling the data inputs to the adder (basic component of an arithmetic circuit), it is possible to obtain different types of arithmetic operations. In the circuit below contains:  4 full-adders  4 multiplexers (controlled by selection inputs S0 and S1)  Two 4-bit inputs A and B and a 4-bit output D  Input carry cin goes to the carry input of the full-adder. Output of the binary adder is calculated from the arithmetic sum: D = A + Y + cin By controlling the value of Y with the two selection inputs S1 & S0 and making cin= 0 or 1, it is possible to generate the 8 arithmetic micro-operations listed in the table below: Table: Arithmetic Circuit Function Table When S1S0 = 00, the value of B is applied to the Y inputs of the adder. If Cin = 0, the output D = A + B. If Cin = 1, output D = A + B + 1. Both cases perform the add micro-operation with or without adding the input carry. When S1S0 = 01, the complement of B is applied to the Y inputs of the adder. If Cin = 1, then D =A +B’+ 1. This produces A plus the 2’s complement of B, which is equivalent to a subtract with borrow, that is, A – B – 1. Downloaded from CSIT Tutor 8 | P a g e b i i z a y @ g m a i l . c o m Table: Sixteen Logic Micro-operations Hardware Implementations and Applications The hardware implementation of logic micro-operations requires that logic gates be inserted for each bit or pair of bits in the registers to perform the required logic function. Although there are 16 logic micro-operations, most computers use only four --- AND, OR, XOR (exclusive-OR), and complement by which all others can be derived. Figure below shows one stage of a circuit that generates the four basic logic micro-operations. It consists of four gates and a multiplexer. Each of the four logic operations is generated through a gate that performs the required logic. The outputs of the gates are applied to the data inputs of the multiplexer. The two selection inputs S1 and S0 choose one of the data inputs of the multiplexer and direct its value to the output. The diagram shows one typical stage with subscript i. For a logic circuit with n bits, the diagram must be repeated n times for i = 0, 1, 2, …, N–1. The selection variables are applied to all stages. The function table lists the logic micro-operations obtained for each combination of the selection variables. Downloaded from CSIT Tutor 9 | P a g e b i i z a y @ g m a i l . c o m Figure: One stage of Logic Circuit Logic micro operations are very useful for manipulating individual bits or a portion of a word stored in a register. They can be used to change bit values, delete a group of bits, or insert new bit values into a register. The following examples show how the bits of one register (designated by A) are manipulated by logic micro-operations as a function of the bits of another register (designated by B). In a typical application, register A is a processor register and the bits of register B constitute a logic operand extracted from memory and placed in register B. The selective-set operation sets to 1 the bits in A where there are corresponding 1’s in B 1010 A before 1100 B (logic operand) 1110 A after A ← A ∨ B The selective-complement operation complements bits in A where there are corresponding 1’s in B 1010 A before 1100 B (logic operand) 0110 A after A ← A ⊕ B The selective-clear operation clears to 0 the bits in A only where there are corresponding 1’s in B 1010 A before 1100 B (logic operand) 0010 A after A ← A ∧ B Downloaded from CSIT Tutor 10 | P a g e b i i z a y @ g m a i l . c o m The mask operation is similar to the selective-clear operation, except that the bits of A are cleared only where there are corresponding 0’s in B 1010 A before 1100 B (logic operand) 1000 A after A ← A ∧ B The insert operation inserts a new value into a group of bits. This is done by first masking the bits to be replaced and then Oring them with the bits to be inserted. 0110 1010 A before 0000 1111 B (mask) 0000 1010 A after masking 0000 1010 A before 1001 0000 B (insert) 1001 1010 A after insertion The clear operation compares the bits in A and B and produces an all 0’s result if the two number are equal 1010 A 1010 B 0000 A ← A ⊕ B Shift Micro-operation Shift micro-operations are used for serial transfer of data. They are also used in conjunction with arithmetic, logic, and other data-processing operations. There are three types of shifts 1. Logical shift 2. Circular shift 3. Arithmetic shift Figure: Shift Micro-operations Downloaded from CSIT Tutor 13 | P a g e b i i z a y @ g m a i l . c o m Hardware implementation of shift micro-operations A bi-directional shift unit with parallel load could be used to implement this. Two clock pulses are necessary with this configuration: one to load the value and another to shift. In a processor unit with many registers it is more efficient to implement the shift operation with a combinational circuit. The content of a register to be shifted is first placed onto a common bus and the output is connected to the combinational shifter, the shifted number is then loaded back into the register. This can be constructed with multiplexers. Downloaded from CSIT Tutor 14 | P a g e b i i z a y @ g m a i l . c o m It has 4 data inputs A0 through A3 and 4 data outputs H0 through H3. There are two serial inputs, one for shift-left (IL) and other for shift-right (IR). When S = 0: input data are shifted right (down in fig). When S = 1: input data are shifted left (up in fig). Arithmetic Logic Shift Unit The arithmetic logic unit (ALU) is a common operational unit connected to a number of storage registers. To perform a micro-operation, the contents of specified registers are placed in the inputs of the ALU. The ALU performs an operation and the result is then transferred to a destination register. The ALU is a combinational circuit so that the entire register transfer operation from the source registers through the ALU and into the destination register can be performed during one clock pulse period. Downloaded from CSIT Tutor 15 | P a g e b i i z a y @ g m a i l . c o m The diagram above shows just one typical stage. The circuit must be repeated n times for an n-bit ALU. i. Input Ai and Bi are applied to both the arithmetic and logic units. A particular micro- operation is selected with inputs S1 and S0. ii. A 4x1 MUX at the output chooses between an arithmetic output in Di and a logic output in Ei. iii. The data inputs to the multiplexer are selected with inputs S3 and S2. iv. The other two data inputs to the MUX receive inputs Ai-1 for the shift right operation and Ai+1 for the shift left operation. v. Cin is the selection variable for the arithmetic operation. vi. The circuit provides eight arithmetic operation, four logic operations and two shift operations. Each operation is selected with the five variables s3, s2, s1, s0 and cin. The input carry cin is used for arithmetic operations only. vii. The table lists the 14 operations of the ALU. The first eight are arithmetic operation and are selected with S3 S2 = 00. The next four are logic operation and are selected with S3 S2 = 01 and last two operation are shift operation and are selected with S3 S2 = 10 and 11. Book References: (1) Andrew S. Tanenbaum, “Structured Computer Organization”, Fourth Edition. (2) M. Morris Mano, “Computer System Architecture”, Pearson, 3rd Ed, 2004. (3) John P. Hayes, “Computer Architecture & Organization”. Web References: (4) http://en.wikipedia.org (5) http://www.cs.uwm.edu/ (6) http://www.transtutors.com/ Downloaded from CSIT Tutor 2 | P a g e b i i z a y @ g m a i l . c o m Instruction Register (IR) Instruction Register (16 bits) holds the instruction code of the instruction currently executing. Outputs of this register are hardwired to specific logic in the control unit, which interprets the bits to generate control signals. Address Register (AR) Address Register (12 bits) is used to interface with the memory unit. All memory-references are initiated by loading the memory address into AR. Temporary Register (TR) Temporary Register (16 bits) is an extra register for storing data or addresses. Input and Output Registers The Basic Computer has one input device and one output device. The Input Register (INPR) holds an 8 bit character gotten from an input device. The Output Register (OUTR) holds an 8 bit character to be send to an output device. Figure: Registers in the Basic Computer Program Counter (PC) The program counter (PC) is commonly called the instruction pointer (IP) in Intel x86 microprocessors, and sometimes called the Instruction Address Register (IAR), or just part of the instruction sequencer in some computers, is a processor register. Program Counter (12 bits) holds memory address of current/next instruction to be executed. Updated as part of the instruction cycle. Usually incremented, but may be parallel loaded by jump/branch instructions. It keeps track of the next memory address of the instruction that is to be executed once the execution of the current instruction is completed. In other words, it holds the address of the memory location of the next instruction when the current instruction is executed by the microprocessor. Downloaded from CSIT Tutor 3 | P a g e b i i z a y @ g m a i l . c o m Accumulator Register (AC) This Register is used for storing the Results those are produced by the System. When the CPU will generate Some Results after the Processing then all the Results will be Stored into the AC Register. Accumulator (16 bits) is used for all mathematical, logic, and shift operations except incrementing and clearing other registers (most have built-in increment and clear capability). It is the destination for all ALU operations, and a source for all dyadic (two-operand) operations. Data Register (DR) A register used in microcomputers to temporarily store data being transmitted to or from a peripheral device. Data Register (16 bits) is used to contain a second operand for dyadic operations such as Add, Sub, AND, OR. Table: List of Basic Computer Registers Internal BUS Structure The registers in the basic computer are connected using a bus. Most registers have load, increment, and clear capabilities built-in. This eliminates the need to use the ALU or the BUS for increment and clear, and hence we can perform these operations on any register in parallel with other micro- operations. AR outputs are the memory address bus. They are directly connected to the address input of the memory unit. AC and DR outputs hardwired into ALU. Hence, operands for dyadic operations such as add, sub, and, or must be in AC and DR. Inputs of INPR are hardwired from the input device. We cannot transfer anything into INPR from the bus. Outputs of INPR are hardwired to ALU. We can only transfer INPR to AC. Outputs of OUTR hardwired to the output device. We cannot transfer from OUTR to the bus. Memory data inputs and outputs are connected directly to the internal bus. Downloaded from CSIT Tutor 4 | P a g e b i i z a y @ g m a i l . c o m Three control lines, S2, S1, and S0 control which register the bus selects as its input. Either one of the registers will have its load signal activated, or the memory will have its write signal activated. The 12-bit registers, AR and PC, have 0’s loaded onto the bus in the high order 4 bit positions. When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8 bits on the bus. Figure: Common BUS System Instruction Codes Instructions are encoded as binary instruction codes. A computer instruction is often divided into two parts:  An opcode (Operation Code) that specifies the operation for that instruction  An address that specifies the registers and/or locations in memory to use for that operation In the basic computer, since the memory contains 4096 (= 212) words, we needs 12 bit to specify which memory address this instruction will use. In the basic computer, bit 15 of the instruction specifies the addressing mode (0: direct addressing, 1: indirect addressing). Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits for the instruction’s opcode. Downloaded from CSIT Tutor 7 | P a g e b i i z a y @ g m a i l . c o m Table: Basic Computer Instructions Instruction Cycle The CPU performs a sequence of micro-operations for each instruction. The sequence for each instruction of the Basic Computer can be refined into 4 abstract phases: 1. Fetch an instruction from memory 2. Decode the instruction 3. Read the effective address from memory if the instruction has an indirect address 4. Execute the instruction After an instruction is executed, the cycle starts again at step 1, for the next instruction. Instruction Fetch and Decode Program execution begins with: PC ← address of first instruction, SC ← 0 After this, the SC is incremented at each clock cycle until an instruction is completed, and then it is cleared to begin the next instruction. This process repeats until a HLT instruction is executed, or until the power is shut off. Downloaded from CSIT Tutor 8 | P a g e b i i z a y @ g m a i l . c o m The instruction fetch and decode phases are the same for all instructions, so the control functions and micro-operations will be independent of the instruction code. Everything that happens in this phase is driven entirely by timing variables T0, T1 and T2. Hence, all control inputs in the CPU during fetch and decode are functions of these three variables alone. For every timing cycle, we assume SC ← SC + 1 unless it is stated that SC ← 0. Figure: Register transfers for the fetch phase The operation D0-7 ← Decode IR(12-14) is not a register transfer like most of our micro-operations, but is actually an inevitable consequence of loading a value into the IR register. Since the IR outputs 12-14 are directly connected to a decoder, the outputs of that decoder will change as soon as the new values of IR(12-14) propagate through the decoder. Note that incrementing the PC at time T1 assumes that the next instruction is at the next address. This may not be the case if the current instruction is a branch instruction. However, performing the increment here will save time if the next instruction immediately follows, and will do no harm if it doesn't. The incremented PC value is simply overwritten by branch instructions. Downloaded from CSIT Tutor 9 | P a g e b i i z a y @ g m a i l . c o m Likewise, loading AR with the address field from IR at T2 is only useful if the instruction is a memory- reference instruction. We won't know this until T3, but there is no reason to wait since there is no harm in loading AR immediately. Determining the Instruction Type By time T2, the opcode has been decoded by the decoder attached to IR(12-14), and the control signals D0-7 are available. At pulse T2, IR(15) is loaded into the I flip-flop. Hence, all of these signals are available for use at pulse T3. D7 indicates that the opcode field is 111, and this is either a register or I/O instruction. (i.e. it is not a memory-reference instruction.) The I bit allows us to distinguish between register and I/O instructions. Figure: Flowchart for instruction cycle D7' indicates a memory-reference instruction. In this case, the I bit determines the addressing mode. What happens at time T3 therefore depends on the two variables D7 and I.  Register-reference: D7I'T3: Execute register-reference instruction.  I/O Reference: D7IT3: Execute I/O instruction.  Memory-reference (Indirect addressing): D7'IT3: AR ← M[AR] Downloaded from CSIT Tutor 12 | P a g e b i i z a y @ g m a i l . c o m Figure: Example of BSA instruction execution Input-Output and Interrupt Hardware Summary The Basic Computer I/O consists of a simple terminal with a keyboard and a printer/monitor. - The terminal sends and receives serial information - The serial information from the keyboard is shifted into INPR - The serial information for the printer is stored in the OUTR - INPR and OUTR communicate with the terminal serially and with the AC in parallel. - The flags are needed to synchronize the timing difference between I/O device and the computer Downloaded from CSIT Tutor 13 | P a g e b i i z a y @ g m a i l . c o m The register reference instructions are recognized by:  D7IT3 = p  IR(i) = Bi, i = 6, …, 11 Table: Input-Output Instructions Interrupts With interrupts, the running program is not responsible for checking the status of I/O devices. Instead, it simply does its own work, and assumes that I/O will take care of itself! When a device becomes ready, the CPU hardware initiates a branch to an I/O subprogram called an interrupt service routine (ISR), which handles the I/O transaction with the device. An interrupt can occur during any instruction cycle as long as interrupts are enabled. When the current instruction completes, the CPU interrupts the flow of the program, executes the ISR, and then resumes the program. The program itself is not involved and is in fact unaware that it has been interrupted. Downloaded from CSIT Tutor 14 | P a g e b i i z a y @ g m a i l . c o m Figure: Flowchart for Interrupt Cycle Interrupts can be globally enabled or disabled via the IEN flag (flip-flop). If interrupts are enabled, then when either FGI or FGO gets set, the R flag also gets set. (R = FGI V FGO) This allows the system to easily check whether any I/O device needs service. Determining which one needs service can be done by the ISR. If R = 0, the CPU goes through a normal instruction cycle. If R = 1, the CPU branches to the ISR to process an I/O transaction. The interrupt cycle is a HW implementation of a branch and save return address operation. At the beginning of the next instruction cycle, the instruction that is read from memory is in address 1. At memory address 1, the programmer must store a branch instruction that sends the control to an interrupt service routine. The instruction that returns the control to the original program is “indirect BUN 0". Figure: Interrupt Cycle demonstration Register Transfer Statements for Interrupt Cycle: R F/F  1 if IEN (FGI + FGO) T0T1T2  T0T1T2 (IEN) (FGI + FGO): R  1 Downloaded from CSIT Tutor 1 | P a g e b i i z a y @ g m a i l . c o m Unit 4 - Control Unit Control Memory Control units that use dynamic microprogramming use a writable control memory. This type of memory can be used for writing (to change the microprogram) but is used mostly for reading. A memory that is part of a control unit is called a control memory. The control unit in a digital computer initiates sequences of micro-operations. The control variables can be represented by a string of 1’s and 0’s called a control word. The control information is shared in a control memory, in a micro-programmed organization. A micro- programmed control unit is a control unit whose binary control variables are stored in memory. Each word in control memory contains within it is a microinstruction. The control memory is programmed to begin the desired sequence of micro-operation. A sequence of microinstructions constitutes a microprogram. When the control signals are generated by hardware, it is hardwired. In a bus-oriented system, the control signals that specify micro-operations are groups of bits that select the paths in multiplexers, decoders, and ALUs. The control memory is usually a ROM, which stores all control information permanently. The control address register (CAR) specifies the address of the microinstruction, and the control data register holds the microinstruction read from memory. Control Unit 5 Hrs. Control Memory 1 Hr. Control Word, Control Memory, Stored Program Organization Hardwired Control 1 Hr. Introduction, Timing and Control, Control Unit of Basic Computer, Timing Signal Micro-programmed Control 2 Hrs. Micro-program Control Organization Address Sequencing  Introduction, Conditional Branching, Mapping of Instructions, Subroutines Micro-programs  Micro-instruction and micro-operation Format, Symbolic microinstructions, Symbolic micro-program, Binary micro-program Design of control unit 1 Hr. F-field Decoding, Micro-program Sequencer Downloaded from CSIT Tutor 2 | P a g e b i i z a y @ g m a i l . c o m Figure: Micro-programmed Control Organization The microinstruction contains a control word that specifies one or more micro-operations for the data processor. Once these operations are executed, the control must determine the next address. The location of the next microinstruction is generally the one next in sequence, otherwise, it may be located somewhere else in the control memory. For this reason it is necessary to use some bits of the present microinstruction to control the generation of the address of the next microinstruction. The next address may also be a function of external input conditions. While the micro-operations are being executed, the next address is computed in the next address generator circuit and then transferred into the control address register to read the next micro-instruction. Hence a microinstruction contains bits for initiating micro-operations in the data processor part and bits that determine the address sequence for the control memory. A microprogram sequencer is the next address generator, as it determines the address sequence that is read from control memory. The address of the next microinstruction can be specified in several ways depending on the sequencer inputs. Typical functions of a microprogram sequencer are:  incrementing the CAR by one  loading into the CAR and address from control memory  transferring an external address  loading an initial address to start the control operations The control data register (CDR) stores the present microinstruction while the next address is computed and read from memory. The data register is also called a pipeline register. It allows the execution of the micro-operations specified by the control word simultaneously with the generation of the next microinstruction. This configuration requires a two-phase clock, with one clock applied to the address register and the other to the data register. The main advantage of the micro-programmed control is that once the hardware configuration is built, there should be no need for further hardware or wiring changes. If we want to make a different control sequence for the system, all we need to do is to specify a different set of microinstructions for control memory. The hardware configuration should not be changed for different operations. We have to change only the microprogram residing in control memory. Downloaded from CSIT Tutor 3 | P a g e b i i z a y @ g m a i l . c o m Timing and Control Timing pulses are used in sequencing the micro-operations in an instruction. A master clock generator is used for controlling the timing for all register in a computer system. A state of a register cannot be changed by a clock pulse until it is enabled by the control signal, which are generated in the control unit and provide control inputs for multiplexers, processor register, and micro-operations. The control organization is of two types; hardwired control and micro- programmed control. Hardwired Control In a hardwired control, the control signals are generated by using the collection of combinational circuits. The main advantage of the hardwired control is that, it can be optimized to produce a fast mode of operation. Whenever a change or modification is to be done in the design, then the wiring among the various components needs to be done. Micro-Programmed Control In a micro-programmed control, a control memory is used for storing control information which is also programmed for initiating the sequence of micro-operations. Whenever any change or modification is required in the design, it can be done by updating the micro-program in the control memory. Control Unit Figure: Control unit of Basic Computer Downloaded from CSIT Tutor 6 | P a g e b i i z a y @ g m a i l . c o m  The control memory then goes through the routine to determine the effective address of the operand. AR holds operand address.  The next step is to generate the micro-operations that execute the instruction by considering the opcode and applying a mapping.  After execution, control must return to the fetch routine by executing an unconditional branch. The microinstruction in control memory contains a set of bits to initiate micro-operations in computer registers and other bits to specify the method by which the next address is obtained. Conditional Branching Conditional branching is obtained by using part of the microinstruction to select a specific status bit in order to determine its condition. The status conditions are special bits in the system that provide parameter information such as the carry-out of an adder, the sign bit of a number, the mode bits of an instruction, and i/o status conditions. The status bits, together with the field in the microinstruction that specifies a branch address, control the branch logic. The branch logic tests the condition, if met then branches, otherwise, increments the CAR. If there are 8 status bit conditions, then 3 bits in the microinstruction are used to specify the condition and provide the selection variables for the multiplexer. If Condition is true, set the appropriate field of status register to 1. Conditions are tested for O (overflow), N (negative), Z (zero), C (carry), etc. Then test the value of that field if the value is 1 take branch address from the next address field of the current microinstruction). Otherwise simple increment the address. Unconditional Branching For unconditional branching, fix the value of one status bit to be one load the branch address from control memory into the CAR. Mapping of Instruction A special type of branch exists when a microinstruction specifies a branch to the first word in control memory where a microprogram routine is located. The status bits for this type of branch are the bits in the opcode. Assume an opcode of four bits and a control memory of 128 locations. The mapping process converts the 4-bit opcode to a 7-bit address for control memory. This provides for each computer instruction a microprogram routine with a capacity of four microinstructions. Another Approach of Mapping Modify opcode to use it as an address of control memory. Downloaded from CSIT Tutor 7 | P a g e b i i z a y @ g m a i l . c o m Mapping Function Implemented by ROM or PLA Use opcode as address of ROM where address of control memory is stored and then use that address as an address of control memory. Subroutines Subroutines are programs that are used by other routines to accomplish a particular task and can be called from any point within the main body of the microprogram. Frequently many micro-programs contain identical section of code. Microinstructions can be saved by employing subroutines that use common sections of microcode. Microprogram Example Once we have a configuration of a computer and its micro-programmed control unit, the designer generates the microcode for the control memory. Code generation of this type is called microprogramming and is similar to conventional machine language programming. The block diagram of computer consists of: Figure: Computer hardware configuration Downloaded from CSIT Tutor 8 | P a g e b i i z a y @ g m a i l . c o m Transfer of information among registers in the processor is through Multiplexers rather than a bus. Two memory units: Main memory – stores instructions and data Control memory – stores microprogram Four processor registers: Program counter – PC Address register – AR Data register – DR Accumulator register - AC Two control unit registers: Control address register – CAR Subroutine register – SBR Three fields for an instruction: I = 1-bit for indirect addressing Opcode = 4-bit Address Field = 11-bit The example will only consider the following 4 of the possible 16 memory instructions Symbol Opcode Description ADD 0000 AC ← AC + M[EA] BRANCH 0001 If (AC < 0) then (PC ← EA) STORE 0010 M[EA] ← AC EXCHANGE 0011 AC ← M[EA], M[EA] ← AC Note: (EA is the effective address) The microinstruction format is composed of 20 bits with four parts: Downloaded from CSIT Tutor 11 | P a g e b i i z a y @ g m a i l . c o m Fig. Decoding of Micro-operation Fields. Three decoders and some of the connections that must be made from their outputs. Each of the three fields of the microinstruction presently available in the output of control memory are decoded with a 3x8 decoder to provide eight outputs.  when F1 = 5, transfers the content of DR(0-10) to AR (DRTAR)  when F1 = 6 there is a transfer from PC to AR (PCTAR)  Outputs 5 and 6 of decoder F1 are connected to the load input of AR so that information is transferred to AR. The multiplexers select the information from DR when output 5 is active and from PC when output 5 is inactive. Because we have 8 micro-operations represented with the help of 3 bits in every table and also we have 3 such tables possible we have decoded these micro-operations field bits with three 3 x 8 decoders. Downloaded from CSIT Tutor 12 | P a g e b i i z a y @ g m a i l . c o m After getting the micro-operations, we have to give it to particular circuits, the data manipulation type of micro-operations like AND, ADD, Sub and so on we give to ALU and the corresponding results moved to AC. The ALU has been provided data from AC and DR. And for data transfer type of instructions like in the case of PCTAR or DRTAR we need to simply transfer the values. Because we have two options for data transfer in AR we are taking the help of MUX to choose one. We will take 2 x 1 MUX and one select line which is attached with DRTAR micro-operation signal. That means if DRTAR is high then MUX will choose DR to transfer the data to AR else PC‘s data will be moved to AR. And the corresponding data movement will be done with the help of load high or not. If any of the values is high the value will be loaded to AR. The clock signal is provided for the synchronization of micro-operations. Instead of using gates to generate the control signals marked by the symbols AND, ADD, and DR. These inputs will now come from the outputs of the decoders associated with the symbols AND, ADD, and DRTAC respectively. The other outputs of the decoders that are associated with an AC operation must also be connected to the arithmetic logic shift unit in a similar fashion. Microprogram Sequencer: The basic components of a micro-programmed control unit are the control memory and the circuits that select the next address. The address selection part is called a micro-program sequencer. It can be constructed with digital functions to suit a particular application. Main purpose is to present an address to the control memory so that a microinstruction may be read and executed. Design of input logic: The input logic circuit in the figure below has three inputs, I0, I1, and T, and three outputs S0, S1, and L. Variables S0 and S1 select one of the source addresses for CAR. Variable L enables the load input in SBR. The binary values of the two selection variables determine the path in the multiplexer. For example, with S1S0 = 10, multiplexer input number 2 is selected and establishes a transfer path from SBR to CAR. Note that each of the four inputs as well as the output of MUX 1 contains a 7-bit address. The truth table can be used to obtain the simplified Boolean functions for the input logic circuit: S1=I1 S0 = I1I0+I’1T L = I’1I0T The circuit can be constructed with three AND gates, an OR gate and an inverter. The truth table for the input logic circuit is shown in table below: Downloaded from CSIT Tutor 13 | P a g e b i i z a y @ g m a i l . c o m Figure: Microprogram Sequencer for a Control Memory Downloaded from CSIT Tutor 2 | P a g e b i i z a y @ g m a i l . c o m 1. A set of registers for holding binary information. 2. An arithmetic and logic unit (ALU) for performing data manipulation, and 3. A control unit that coordinates and controls the various operations and initiates the appropriate sequence of micro-operations for each task. Computer instructions are normally stored in consecutive memory locations and are executed in sequence one by one. The control unit allows reading of an instruction from a specific address in memory and executes it with the help of ALU and Register. All the arithmetic and logical Operations are performed in the CPU in special storage areas called registers. The size of the register is one of the important considerations in determining the processing capabilities of the CPU. Register size refers to the amount of information that can be held in a register at a time for processing. The larger the register size, the faster may be the speed of processing. The register set stores intermediate data used during the execution of the instructions. The arithmetic logic unit (ALU) performs the required micro-operations for executing the instructions. The control unit supervises the transfer of information among the registers and instructs the ALU as to which operation to perform. General Register Organization The number and the nature of registers is a key factor that differentiates among computers. For example, Intel Pentium has about 32 registers. Some of these registers are special registers and others are general-purpose registers. The general-purpose registers as the name suggests can be used for various functions. For example, they may contain operands or can be used for calculation of address of operand etc. When a large number of registers are included in the CPU, it is most efficient to connect them through a common bus system. The registers communicate with each other not only for direct data transfers, but also while performing various micro-operations. Hence it is necessary to provide a common unit that can perform all the arithmetic, logic, and shift micro-operations in the processor. Why we need CPU registers? During instruction execution, we could store pointers, counters, return addresses, temporary results and partial products in some locations in RAM, but having to refer memory locations for such applications is time consuming compared to instruction cycle. So for convenient and more efficient processing, we need processor registers (connected through common bus system) to store intermediate results. A bus organization for seven CPU registers is shown in figure below. The output of each register is connected to two multiplexers (MUX) to form the two buses A and B. The selection lines in each multiplexer select one register or the input data for the particular bus. The A and B buses form the inputs to a common arithmetic logic unit (ALU). The operation selected in the ALU determines the arithmetic or logic micro-operation that is to be performed. Downloaded from CSIT Tutor 3 | P a g e b i i z a y @ g m a i l . c o m The result of the micro-operation is available for output data and also goes into the inputs of all the registers. The register that receives the information from the output bus is selected by a decoder. The decoder activates one of the register load inputs, thus providing a transfer path between the data in the output bus and the inputs of the selected destination register. For example, to perform the operation R1 ← R2 + R3 the control must provide binary selection variables to the following selector inputs: 1. MUX A selector (SELA): to place the content of R2 into bus A. 2. MUX B selector (SELB): to place the content of R3 into bus B. 3. ALU operation selector (OPR): to provide the arithmetic addition A + B. 4. Decoder destination selector (SELD): to transfer the content of the output bus into R1 Figure: Register set with common ALU Downloaded from CSIT Tutor 4 | P a g e b i i z a y @ g m a i l . c o m Control Word There are 14 binary selection inputs in the unit, and their combined value specifies a control word. The 14-bit control word is defined in figure below. Figure: Control Word It consists of four fields. Three fields contain three bits each, and one field has five bits. The three bits of SELA select a source register for the A input of the ALU. The three bits of SELB select a register for the B input of the ALU. The three bits of SELD select a destination register using the decoder and its seven load outputs. The five bits of OPR select one of the operations in the ALU. The 14-bit control word when applied to the selection inputs specify a particular micro-operation. Table: Encoding of register selection fields Table: Encoding of ALU operations Downloaded from CSIT Tutor 7 | P a g e b i i z a y @ g m a i l . c o m Push Operation: A new item is inserted with the push operation as follows: SP ← SP - 1 M[SP] ← DR POP Operation: A new item is deleted with a pop operation as follows: DR ← M[SP] SP ← SP + 1 Figure: Computer memory with program, data, and stack segments Instruction Formats Instruction format is the function of the control unit within the CPU to interpret each instruction code. The bits of the instruction are divided into groups called fields. The most common fields are: 1. Operation code field – Specifies the operation to be performed. 2. Address field – Designates a memory address or a processor register 3. Mode field – specifies the way the operand or effective address is determined A register address is a binary number of k bits that defines one of 2k registers in the CPU. • The instructions may have several different lengths containing varying number of addresses. The number of address fields in the instruction format of a computer depends on the internal organization of its registers. Downloaded from CSIT Tutor 8 | P a g e b i i z a y @ g m a i l . c o m Processor Organization Most computers fall into one of the three following processor organizations: 1. Single Register (Accumulator) organization 2. General register organization 3. Stack organization The Single Register (Accumulator) Organization uses one address field. Example: ADD X, where X is the address of the operand. The ADD instruction results in operation AC ← AC + M[X], where AC is the accumulator register and M[X] denotes memory word located at address X.  Basic Computer is a good example  Accumulator is the only general purpose register  Uses implied accumulator register for all operations The General Register Organization uses three address fields. Example: ADD R1, R2, R3, where R1, R2, and R3 are the registers. The above ADD instruction results in the operation R1 ← R2 + R3  Used by most modern processors  Any of the registers can be used as the source or destination for computer operations. The Stack Organization would require one address field for PUSH/POP operations and none for operation-type instructions. Example: PUSH X, which pushes the word at address X on top of the stack. The instruction ADD in a stack computer consists of opcode only with no address field.  All operations are done with the stack  For example, an OR instruction will pop the two top elements from the stack, do a logical OR on them, and push the result on the stack. Downloaded from CSIT Tutor 9 | P a g e b i i z a y @ g m a i l . c o m Types of Instruction Instruction format of a computer instruction usually contains 3 fields: operation code field (opcode), address field and mode field. The number of address fields in the instruction format depends on the internal organization of CPU. On the basis of no. of address field we can categorize the instruction as below: Three-Address Instructions Computers with three-address instruction formats can use each address field to specify either a processor register or a memory operand. Example: X = (A+B) * (C + D) ADD R1, A, B // R1 ← M [A] + M [B] ADD R2, C, D // R2 ← M[C] + M [D] MUL X, R1, R2 // M[X] ← R1 * R2 It is assumed that the computer has two processor registers, R1 and R2. The symbol M[A] denotes the operand at memory address symbolized by A. The advantage of the three-address format is that it results in short programs when evaluating arithmetic expressions. The disadvantage is that the binary-coded instructions require too many bits to specify three addresses. Two-Address Instructions These instructions are most common in commercial computers. Here again each address field can specify either a processor register or a memory word. Example: X = (A+B) * (C + D) MOV R1, A // R1 ← M [A] ADD R1, B // R1 ← R1 + M [A] MOV R2, C // R2 ← M[C] ADD R2, D // R2 ← R2 + M [D] MUL R1, R2 // R1 ← R1 * R2 MOV X, R1 // M[X] ← R1 The MOV instruction moves or transfers the operands to and from memory and processor registers. The first symbol listed in an instruction is assumed to be both a source and the destination where the result of the operation is transferred. One-Address Instructions One-address instruction uses an implied accumulator (AC) register for all data manipulation. All operations are done between AC and memory operand. Example: X = (A+B) * (C + D) LOAD A // AC ← M [A] ADD B // AC ← AC + M [B] STORE T // M [T] ← AC Downloaded from CSIT Tutor 12 | P a g e b i i z a y @ g m a i l . c o m Figure: Register Indirect Addressing Mode Autoincrement (or Autodecrement) Addressing Modes: It is similar to register indirect mode except that the register is incremented or decremented after (or before) its value is used to access memory. When address stored in the register refers to a table of data in memory, it is necessary to increment or decrement the register after every access to the table. Direct Addressing Mode: In this mode the effective address is equal to the address part of the instruction. Instruction specifies the memory address which can be used directly to access the memory. The operand resides in memory and its address is given directly by the address field of the instruction. EA= IR (address). Figure: Direct Addressing Mode In a branch-type instruction the address field specifies the actual branch address. Example: ADD A — Adds contents of cell A to accumulator — Look in memory at address A for operand Indirect Addressing Mode: In this mode the address field of the instruction gives the address where the effective address is stored in memory i.e. the address field of an instruction specifies the address of a memory location that contains the address of the operand. Control fetches the instruction from memory and uses its address part to access memory again to read the effective address. EA= M[IR (address)]. Downloaded from CSIT Tutor 13 | P a g e b i i z a y @ g m a i l . c o m Figure: Indirect Addressing Mode Displacement Addressing Mode: A very powerful mode of addressing combines the capabilities of direct addressing and register indirect addressing. The effective address is EA = A + (R) Figure: Displacement Addressing Mode Relative Addressing Modes: The Address field of an instruction specifies the part of the address which can be used along with a designated register (e.g. PC) to calculate the address of the operand. - Address field of the instruction is short - Large physical memory can be accessed with a small number of address bits Three different relative addressing modes exists: 1. PC Relative Addressing Mode: EA = PC + IR(address) 2. Indexed Addressing Mode: EA = IX + IR(address) { IX is index register } 3. Base Register Addressing Mode: EA = BAR + IR(address) Numerical Example of Addressing Modes We have 2-word instruction “load to AC” occupying addresses 200 and 201. First word specifies an operation code and mode and second part specifies an address part (500). Mode field specify any one of a number of modes. For each possible mode we calculate effective address (EA) and operand that must be loaded into AC. Downloaded from CSIT Tutor 14 | P a g e b i i z a y @ g m a i l . c o m Figure: Numerical Example for Addressing Modes Direct addressing mode: EA = address field 500 and AC contains 800 at that time. Immediate mode: Address part is taken as the operand itself. So AC = 500. (Obviously EA = 201 in this case) Indirect mode: EA is stored at memory address 500. So EA=800. And operand in AC is 300. Relative mode:  PC relative: EA = PC + 500=702 and operand is 325. (since after fetch phase PC is incremented)  Indexed addressing: EA=XR+500=600 and operand is 900. Register mode: Operand is in R1, AC = 400 Register indirect mode: EA = 400, so AC=700 Autoincrement mode: Same as register indirect except R1 is incremented to 401 after execution of the instruction. Autodecrement mode: Decrements R1 to 399, so AC is now 450. Downloaded from CSIT Tutor