Exam 1 Solutions - Advanced VLSI Design and Applications | ECEN 6263, Exams of Electrical and Electronics Engineering

Download Exam 1 Solutions - Advanced VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2005 Exam | WRITE YOUR NAME HERE A Aswef All questions must be answered on test paper! Open Book, Open Notes 1, Sketch a transistor leve] circuit diagram for a register using the clocking strategies given below. Assume that the four clock lines, by 4, 2, b,, are available, but not all of them need to be used. The register outputs should change only on the rising edge of 6). Clearly label the D input, Q output, and any clock inputs that you use. a. True single phase clocking uo ft 5 ae “a iJ op ae Pipi. 2 b.Pseudo single phase clocking, : g YQ LL t | D rt Ain 8 ¢. True two phase clocking fo Le { af hk me riera p SUT Ua 4 7a d.Pseudo two phase clocking ie b, ECEN 6263 Fall 2005 Exam 1 October 7, 2005 1 2. For the circuit below, CLK t CLE vo Vi ri Ve V3 ya —l- tC cov T a ayy c3 “Yea ax Vv ax Vv CLE a fill in the timing diagram for the node voltages V1, ..., V4. Be sure to clearly label the steady state voltage in each time interval in terms of Vdd, GND, V,;,, aud. Vip. You may assume that V0=0 fort <0. CLK T I ' f - \ "Vdd \|GND /| Vdd \!}GND /! vad \! GND F ! vo A | | i GND /\oxp / | Vdd ‘\ eyb/ \ayp mt Py a - 1 SL oto TN 1 b.Determine the activity factor, o, of each node (assume a glitch counts as a rise transi- hay tion and a fall transition). } IY a0=_! at=t/2 02-4 3-4 oa =! fo c.Using the activity factors above, and assuming that all capacitances can be ignored except those shown, what is the dynamic power consumption for the circuit? - 2 P=%XCyof VF a ak 2 cy Ps eMart 4 hauler LG Mat 5 Ue tt EC yt B§Cy +O tee t Peas] Ut ECEN 62¢4Pull 2005 Exam 1 Z histor 7, 2005 2