Exam 2 Questions with Solutions - Advanced VLSI Design and Applications | ECEN 6263, Exams of Electrical and Electronics Engineering

Download Exam 2 Questions with Solutions - Advanced VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2005 Exam 2 WRITE YOUR NAME HERE A AS wet All questions must be answered on test paper! Open Book, Open Notes 1. The layout below is for a transistor designed with submicron design rules which require a 3X spacing between poly lines making smaller doglegs in the poly lines. The dogleg portion (shown in the small box) has an approximate resistance/conductance of 1 square. Ol metal 1 i contact poly active gate source drain . What is the channel resistance of this wansistor? Express your answer in terms of the Ww channel sheet resistance, 2,,,, and the grid spacing 4. ~ 40 \ E115 G) Rin = FE ECEN 6263 Fail 2005 Exam 2 November 28, 2005 page | of + 2. Analyze the static RAM memory cell with a single sided write as shown below. I Ww write bit line val CS ay mil} aaa Mé W vs Use the simplified transistor model that was used in class to analyze the double sided memory cells. This model is different than used last year and can be written as 0 Fes <Vr, Iq = 4 4nF Vs Vos > Vow Fos < (es Vira) (an GVes-¥ rq) Vos > Prin Mpg > Vas— Pra) a, 0 Vos? Voy Thy = 1% GK ps Veg <Vips Mog > Vos — Vt) a, Ges— rp) Vas < Vip Vag <(Vas—V rp) ap a. What is the inverter switching valine. Vinv, of the inverter formed by M1 and M2? (Hint: both FETs shoyd be in satur; Pry = D n Ws, (Yay ‘n) =°6, Mw Via ~ Vip ) sree Viaw * 6 Ve, "Ga { Mat “lV, vl) ‘ ECEN 6263 Fall 2005 Exam 2 November 28, 2005 page 2 of 4