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Exam 2 with Solution for Advanced VLSI Design and Applications | ECEN 6263, Exams of Electrical and Electronics Engineering

Material Type: Exam; Professor: Johnson; Class: ADV VLSI DES & APP; Subject: Electrical and Computer Engineering ; University: Oklahoma State University - Stillwater; Term: Fall 2001;

Typology: Exams

2010/2011

Uploaded on 07/17/2011

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Download Exam 2 with Solution for Advanced VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2001 Exam 2 WRITE YOUR NAME HERE All questions must he answered on test paper! Open Book, Open Notes . Estimate the delays in the circuit below using the RC mode] developed in class includ- ing the effects of the transistor threshold voltages 7, and Vz). Use as parameters the channel sheet resistances, the widths of the transistors, ’,, .... Wo, and the node capac itances, Cj, ..., Cs. You may assume that the capacitances already contain all parasitics from the transistors and interconnect. M1 V3 " “s—p 4 me Fo) Fes 4 M3 V4 Note: this circuit is not well designed and should not be used in practice. FCEN 6263 Fall 2003 Exam 2 November 14, 2001 a. Sketch the voltage waveforms for V3, M4, V5 and ¥%— when Vand V2 are as shown below, Show the value of the voltages in the diagram. Find initial values for V3, Vs, V5 and V% by assuming that ¥\(0) = 0, Vo(t} = Vag for t<0. cl Hk fay Vay (4) Cut t —— "WT Gg {@ Fad \ Gua t ¥; Vag \ @) Vote t Vy \ Vue ond t v, Gnd Via - Ven : vst —— | os fa , vet pee \e = : at vad 1 , Whatis the delay from V/, to V3 when F gocs from low to high (transistion (2) in the figure)? R Miata = / g "oe af ») 4yF Sug c Maa +(Re. Rit ¢ 4 an e mn we 3 v c abv, fe 43,7 Ras ¢ Vdd ’ x “Jd~Ve\ R wt t/Ens 2 we tf ne } 2 VMs Fe q NC CEN 6263 Fall 2001 Exam 2 November 14, 200 3, Amswer the questions below for the following layout (all dimensions in A), drain gate source with the following capacitive parameters: OE...) (DQG). and the following sheet resistive parameters: Rye Ryp Rap Rose Ryp Bom Answer the following only for the part of the layout shown above. a. Whal is the effective channel width? 5 ay 5 ky Yar = II (% +g t y b. What is the channel — when the transistor is passing a low signal? p Ret Rap Zs DEnd 1 c. What is the capacitance of the gate node?” Cacti 2 (By (2 +22 27429) + C BY pO q z, ay) LY {| bat + pl LA OLN 6263 Fall 2004 Bram 2 Navember £4, 2001 5 p> ) (rarer 29x) Fe x d. What is the capacitance of the source node? CSunes = End) ( ZAK TD AD ATAXYD EL 4 Yay ase) Re N dye Arbar a thntasat TaD * fad) (San + 2A UP a Laud) yp Ud ne "hs Pp =) {7axr) “Cas (24402 + RA 2? y in ® zayr e, What is the capacitance of the drain node? Crane wo ERR i519) cs 2K t Geese Lon my (sn 48>) lod 20 BCEN 6268 Fall 2001 Exam November 14, 2001 6
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