Computer Organization: CSCI 2150 Test 3 - Fall Semester, 2004 - Prof. David L. Tarnoff, Exams of Computer Architecture and Organization

Download Computer Organization: CSCI 2150 Test 3 - Fall Semester, 2004 - Prof. David L. Tarnoff and more Exams Computer Architecture and Organization in PDF only on Docsity! Points missed: _____ Student's Name: _________________________________ Total score: _____ /100 points East Tennessee State University Department of Computer and Information Sciences CSCI 2150 (Tarnoff) – Computer Organization TEST 3 for Fall Semester, 2004 Read this before starting! • The total possible score for this test is 100 points. • This test is closed book and closed notes. • All answers must be placed in space provided. Failure to do so may result in loss of points. • 1 point will be deducted per answer for missing or incorrect units when required. No assumptions will be made for hexadecimal versus decimal, so you should always include the base in your answer. • If you perform work on the back of a page in this test, indicate that you have done so in case the need arises for partial credit to be determined. • Calculators are not allowed. Use the tables below for any conversions you may need. Leaving numeric equations is fine too. • The table of assembly language commands is on the last page of this test. Remove it if you wish to have better access to it. Use the backside of it as your scrap paper. Turn it in with your test. Binary Hex Binary Hex Power of 2 Equals 0000 0 1000 8 23 8 0001 1 1001 9 24 16 0010 2 1010 A 25 32 0011 3 1011 B 26 64 0100 4 1100 C 27 128 0101 5 1101 D 28 256 0110 6 1110 E 29 512 0111 7 1111 F 210 1K 220 1M 230 1G “Fine print” Academic Misconduct: Section 5.7 "Academic Misconduct" of the East Tennessee State University Faculty Handbook, June 1, 2001: "Academic misconduct will be subject to disciplinary action. Any act of dishonesty in academic work constitutes academic misconduct. This includes plagiarism, the changing of falsifying of any academic documents or materials, cheating, and the giving or receiving of unauthorized aid in tests, examinations, or other assigned school work. Penalties for academic misconduct will vary with the seriousness of the offense and may include, but are not limited to: a grade of 'F' on the work in question, a grade of 'F' of the course, reprimand, probation, suspension, and expulsion. For a second academic offense the penalty is permanent expulsion." 1. How many latches does a 256 Meg SRAM with 8 data bits per location require? Leave your answer in the form of an equation with numeric values. (2 points) There are 256 Meg locations in a 256 Meg SRAM. (256 × 1 Meg = 28 × 220 = 228) Since there are 8 data bits per location, a 256 Meg SRAM contains 228 × 8 = 231 = 2,147,483,648 latches. (Note: you are not responsible for any of the mathematical calculations. Simply putting 256 Meg × 8 would have been sufficient.) 2. Circle all that apply. A storage cell in a DRAM: (4 points) a.) is volatile b.) is a capacitor c.) is cheaper than a cell in an SRAM d.) is a latch e.) must be refreshed regularly f.) is smaller than a cell in an SRAM g.) is typically used for cache RAM h.) is faster than a cell in an SRAM 3. Match each of the settings of the bus control signals R and W on the left with the bus operation on the right. (4 points) R W Operation of the bus 0 0 Processor reads from memory 0 1 Illegal setting 1 0 The bus is idle 1 1 Processor writes to memory 4. What are the high and low addresses (in hexadecimal) of the memory range defined with the chip select shown to the right? (6 points) There are 18 address lines. This is found by noting that the highest address line has a subscript of 17 and therefore, since we begin counting at 0, we know that there are 18 address lines. Looking at the inputs to the NAND gate, we see that to set ^CS to zero, their values must be: A17=1, A16=1, A15=0, and A14=0. Therefore, the address lines have the following values for the high and low address: Low address: 11 0000 0000 0000 00002 = 3000016 High address: 11 0011 1111 1111 11112 = 33FFF16 5. For the chip select in the previous problem, how big is the memory chip that uses this chip select? (3 points) There are 14 address lines that go to the address inputs of the memory chip. Therefore, there are 214 possible addresses meaning that the memory chip has 214 = 24 × 210 = 16K memory locations. A17 A16 A15 A14 CS Now if we insert the tag, line id, and word id of the location holding 5616, we get the following address. 9 bits 8 bits 3 bits 110011010 01100100 110 Converting this address to hex gives us: 1100 1101 0011 0010 0110 = CD32616 14. A block containing the address 6533B16 is not contained in this cache. When loaded, which row (a through f) and column (0 through 7) will its value be stored in? (4 points) Begin by converting this address to binary: 6533B16 = 0110 0101 0011 0011 1011 Now if we partition our address into the components shown in our table, we should see the different values assigned to each parameter. 9 bits 8 bits 3 bits 011001010 01100111 011 The column can be determined from the word id bits: column 011 = column 3 For the row, simply determine which row corresponds to the line number 01100111: 26 + 25 + 22 + 21 + 20 = 64 + 32 + 4 + 2 + 1 = 10310. = row e 15. True or false: A split cache system uses two caches, one for data and one for code. (2 points) This is true. The other type of multiple cache systems uses levels, typically one inside the processor (Level 1) and one on the circuit board close to the processor (Level 2). 16. What is the purpose of pipelining? (3 points) The purpose of pipelining is the improve the performance of the processor by making sure that no component is ever idle. If the hardware that fetches the next instruction can be fetching while the instruction decoder is decoding, then by all means do it. It will save time in the long run. 17. Assume a processor takes 3 cycles to execute any instruction (fetch, decode, execute) a. How many cycles would a non-pipelined processor take to execute 6 instructions? (2 points) A non-pipelined processor simply executes the instructions one at a time with no overlap. Therefore, the number of cycles equals 3 times the number of instructions: number of cycles = 3 x 6 = 18 cycles b. How many cycles would a pipelined processor take to execute 6 instructions? (2 points) A pipelined processor overlaps 2 cycles for each instruction. Therefore, it will take 2 cycles to fill the pipeline, then one cycle per instruction to execute each one. Answer questions 18 through 23 using the following settings of the 8086 registers. AX = 0180h IP = 2122h CS = 6000h BX = AA55h SP = 4344h SS = 7000h CX = 03C0h DI = 6566h DS = 8000h DX = FFEEh BP = 1234h ES = 9000h 18. What is the value contained in the register BL? (2 points) BL is the lower half (byte) of BX. Therefore, the value in BL is 55h. 19. What is the physical address pointed to by ES:BP? (3 points) ES contains the segment address and BP contains the pointer address. To figure out the physical address, begin by converting the 16-bit value in ES to the 20 segment address by adding a hex 0 to the end of the segment value (4 binary 0's). ES = 9000h the segment address is 90000h (notice the added zero) The pointer value (BP in this case) can then be added as an offset to the segment address. 90000 + 1234 ------- 91234 Therefore, the physical address pointed to by ES:BP (9000:1234) is 91234h. 20. True or false: The physical address of the next instruction to be executed by the processor can be calculated from the above data? (2 points) The answer is true. The physical address of the next instruction to execute is determined from the values contained in CS and IP (CS:IP). Since both of those values are present above (CS:IP = 6000:2122), then we can calculate the physical address of the next instruction to execute. 21. What is the value of SP after the execution of the instruction PUSH AX? (2 points) If you go to the list of instructions on the last page, you'll see that executing a PUSH instruction "decrements SP by the size of the operand (two for 8 or 16 bit and four for 32 bit increments). Since AX is a 16 bit value, SP is decremented by 2 giving us 4344h – 2 = 4342h. 22. Assume that the instruction INC DH is executed. How would the following flags be set? Write "N/A" if the flag was not affected. (3 points) Referring to the list of instructions on the last page, we see that the INC adds 1 to the operand and affects the flags CF, AF, OF, PF, SF, and ZF. Since DH equals FF16 before the instruction is number of cycles = 2 + 6 = 8 cycles executed, it equals 0016 after the instruction is executed. Therefore, since it is equal to zero, the zero flag (ZF) is set to 1. Since zero is considered a positive value (the MSB of the result is 0), the sign flag (SF) is cleared to 0. Adding 1 to FF also generates a carry. Therefore, CF = 1. ZF = __1__ CF = __1__ SF = __0__ 23. Assume that the instruction SAR BH,3 is executed. What would the new value of BH be? (3 points) Referring to the list of instructions on the last page, we see that the SAR BH,3 will shift the 8-bit BH register 3 places to the right with the most significant bit duplicated to fill in the spaces left by the right shifts. In addition, the carry flag contains the last bit shifted out. So what does BH equal before the instruction? BH = AAh = 10101010b After the instruction, the three right most bits are shifted out, the last one, a zero, going into the carry flag (CF). The most significant bit, a one, is duplicated three times filling in from the left. new BH = 11110101b = F5h SAR modifies the flags CF, OF, PF, SF, and ZF. Since the new value of BH is not equal to zero, the zero flag (ZF) is cleared to 0. Since it is a negative value (the MSB of the result is set to 1), then the sign flag (SF) equals 1. Last of all, the last bit shifted out is in CF which is a zero. ZF = __0__ CF = __0__ SF = __1__ 24. Assume AX=1000h, BX=2000h, and CX=3000h. After the following code is executed, what would AX, BX, and CX contain? (3 points) Place your answers in space below: PUSH CX PUSH BX AX = old CX = 3000h PUSH AX POP CX BX = old BX = 2000h POP BX POP AX CX = old AX = 1000h 25. Which of the following best describes the operation of the instruction MOV AX, [1000h]? (2 pts) a.) Load the 16-bit register AX with the number 100016. b.) Store the value currently held in the 16-bit register AX to the address 100016. c.) Load AX with the value stored at address 100016. d.) Load AX with the value stored at address pointed to by the value stored at the address 100016. e.) None of the above, this is an illegal instruction.