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Exam with Answers Key - Advanced VLSI Design and Applications | ECEN 6263, Exams of Electrical and Electronics Engineering

Material Type: Exam; Professor: Johnson; Class: ADV VLSI DES & APP; Subject: Electrical and Computer Engineering ; University: Oklahoma State University - Stillwater; Term: Fall 2009;

Typology: Exams

2010/2011

Uploaded on 07/17/2011

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Download Exam with Answers Key - Advanced VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263 Fall 2009 Exam 2 WRITE YOUR NAME HERE § AlAsiv-v All questions must be answered on test paper! Open Book, Open Notes 1, The delays for a two input NAND gate were calculated in the notes as follows. A BI|Y ‘ tgp/At Rout R Waa 1 Wa 2 4 Ct DF ng + Wit Wop) SA BT pA” pb} Won + Koa Wool + 2KW in Wap 1i+ C+ N44 24 3+ Wat Wop) 4 K\W na ~ ¥ nal + KW 4 Walt 3K Win W, , min,“ min Wis Woe a Wa Waa Loi t | GG st 2¥ iat Wat Won) 4 Koa ~F nal + KP ya — Wal + 3KW sig a pa py min min ECEN 6263 Fall 2009 Exam 2 November 13, 2009 page 1 of 6 typ/At RoudR ! 2 C+ K)\F,3 + ¥4+ Wop) ee pg Spd pp) + + + Waa |W 4~ Won] + 2KW pig ps pe ain Was (+KQ\V 3+ 4+ Wp) Wig K|W4—W, a + 2KW in Wap W W in i min, “' min Wa Wap +Wayt Wp) +H) A ng t Moat W, + Ws K|Wy4—Wop| + 2K W in LBA pay min Wop 2 Poin ECEN 6263 Fall 2009 Exam 2 November 13, 2009 page 2 af 6 2. Two NOR gates are connected as shown. A2 Al B2 1 Y Bl B2 —4 Bld aa df Bed ell, op Sons Assume that the delays for each gate are as follows (each gate has equal size nFETs and pFETS and 1/ parasitic delay terms are neglected). A BY Cif tap/At Roy fR to 7 501+ K)2+32) (+2) + o/t W 31+ 4 +42) ss Dain min o tlt) F | ja+merg wan o vit re 2a + K(4422) 4042) Faia a. Find the falling output path delay, tapate from A2 to Y in tems of K, Z;, 2, W1, \~ We and Cioag- bag pam = Edgy * SOD = A ar ye, + tara = &(8) (2432 ate aay YW eR C ipa FB (iaeylyia) + 10 1 Dt : ton Re ECEN 6263 Fall 2009 Exam 2 ‘November 13, 2009 page 5 of 6 e b. Find the rising output path delay, tap ATH: from A2 to Y in terms of K, 2, Z>, W,, Wy iv and Cigad- Lis pm = far) x bur = &l (ree) Gane at p (AS) 2) Ter ® amd (homens pm) a 4 c. If the transistors in gate 2 are all minimum size (Wy. = Wr = Wonin), What are Zy and Wy? Bre Whi, 2 WR ge S| we Wray = We mis a AS = 2 Man 1 d. With the above choices for Z) and W, find Z; so that the parasitic rise/fall path delays are equal (‘app aT = tapPaTH)- 4 corks Cl pg path= BU) (2432) at + z HEYMAN) at fem bs be pat 2 ZH (ne)lards)at 4 y (ad) (23a) ae %, l wrthy 252) Wet (2tge,) $2040 (449) > Z(rBlareas + LoOi2) 32h.+ | 4b = ers + Elz, 7 32+ 132,-[b =0 Bc BEV BAA BNE ={ SSS oo e. With the above choices for Z;, Z> and W., find W, that minimizes the effort fall path ae delay, tgrpaty- Hint: find 8, = : WilW. a = al 4lMZt oy. bt 4 i tder 24 ee > 8S, . . We Wray bay my atte Lela, Re foe bop ry < Clee, Algo bgorx hee = (ue yd = “Hy _ ui 7 Bh “yd Sg 2 UNS x 1b os BS sor roe bbe st it Adppe T Adee, = 1 Vm - | ozw Ca 3S = a, i rE 3T, ECEN 6263 Fall 2009 Exam 2 November 13, 2009 ‘ oe at - page 6 of 6
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