Download Design Project: Building a Low-Noise Feedback Amplifier Circuit - Prof. William Leach and more Study Guides, Projects, Research Electrical and Electronics Engineering in PDF only on Docsity! 7. DESIGN PROJECT–FALL 2006 7.1 Objective The objective of this experiment is to design, simulate, evaluate experimentally, and docu- ment a low-noise feedback amplifier circuit. The equivalent input noise of the amplifier is to be minimized. 7.2 Specifications The topology used for the feedback amplifier is two internal stages of voltage gain. The first stage is to be discrete. The second stage may be either discrete or an op amp. The specifications for the feedback amplifier are: • DC Power Supplies: either ±15V • Closed Loop Voltage Gain: 30 dB • Maximum Input Signal 200mV • Lower Half-Power Frequency: 20Hz or less • Upper Half-Power Frequency: 20 kHz or greater • THD (total harmonic distortion): less than 0.4% corresponding to an output signal level of +10dBm for an input sine wave with a frequency of 2 kHz • Source Resistance: 10 kΩ • Load Resistance: 600Ω • Noise voltage over the band 20Hz to 20 kHz ≤ 1µV. 7.3 Simulation The initial design should be verified with a SPICE simulation. This simulation must precede the circuit assembly. DESIGN PROJECT–FALL 2006 1 Should the designer elect to employ a BJT as the first stage, the default values for IS, BF, RB, VA, CJC, CJE, and TF for the BJT transistor are not to be used for the simulation. Instead, use the values obtained from curve tracer measurements or manufacturers’ data sheets. The value of the base spreading resistance measured in a previous experiment is to be used as RB. (In determining the optimum collector current use an average or typical value that was measured for the transistor.) A noise simulation of the circuit should be made which predicts the signal-to-noise ra- tio corresponding to an output signal level of +10dBm into 600Ω and noise figure of the amplifier. The SPICE analyses should include .OP (to verify the biasing ), .AC (to verify the fre- quency response specifications and phase margin specifications), .TRAN (to examine the clip- ping and slew rate performance), .FOUR (to verify the distortion specification), and .NOISE (to verify the noise specifications). 7.4 Experimental Measurements Assemble the designed circuit on a solderless breadboard with a 600Ω load resistor. Use a power supply decoupling network. Use the laboratory equipment to measure and record the circuit: • mid-band voltage gain • − 3 dB bandwidth • positive and negative slew rates • distortion @ f = 2kHz • quiescent operating point • output DC offset with input grounded • equivalent input noise voltage • signal-to-noise ratio • noise figure (spot noise figure @ f = 2kHz and the total noise figure) The noise measurements are made with the source grounded. The other measurements are made with the function generator as the source. 2 DESIGN PROJECT–FALL 2006
