Docsity
Docsity

Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity


Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan


Guidelines and tips
Guidelines and tips

Features of CMOS Circuits-Introduction to Microelectronic Circuits-Lecture 27 Slides-Electrical Engineering, Slides of Microelectronic Circuits

This course is taught in University of California, covers the fundamental circuit concepts and analysis techniques in the context of digital electronic circuits. Transient analysis of CMOS logic gates; basic integrated-circuit technology and layout are also included. Features of CMOS Circuits, CMOS Circuits, Noise Margins, Power Dissipation, Current Flow, Switching, Direct Path Current, N Channel, MOSFET, Operation, P Channel, Pull Down, Pull Up, Devices, CMOS NAND Gate, CMOS NOR Gate, CMOS Pass

Typology: Slides

2011/2012

Uploaded on 02/27/2012

elmut
elmut 🇺🇸

4.6

(17)

45 documents

1 / 6

Toggle sidebar

Related documents


Partial preview of the text

Download Features of CMOS Circuits-Introduction to Microelectronic Circuits-Lecture 27 Slides-Electrical Engineering and more Slides Microelectronic Circuits in PDF only on Docsity! 1 Lecture 27, Slide 1EECS40, Fall 2003 Prof. King Lecture #27 ANNOUNCEMENTS • Extra Office Hours this week: – Prof. King: Thu. 10/30 1:15-2 PM – Steve: Fri. 10/31 12-2 PM – Farhana: Sat. 11/1 4-5 PM; Sun. 11/2 3-5 PM (regular office hours cancelled next week) OUTLINE – The CMOS inverter (cont’d) – CMOS logic gates – The body effect Reading (Rabaey et al.) Chapter 5.5.1 (p.174); 6.2.1 (pp.199-202); Chapter 3.3.2 (pp.58-60) Lecture 27, Slide 2EECS40, Fall 2003 Prof. King Features of CMOS Circuits • The output is always connected to VDD or GND in steady state → Full logic swing; large noise margins → Logic levels are not dependent upon the relative sizes of the devices (“ratioless”) • There is no direct path between VDD and GND in steady state → no static power dissipation 2 Lecture 27, Slide 3EECS40, Fall 2003 Prof. King The CMOS Inverter: Current Flow during Switching VIN VOUT VDD VDD0 0 N: off P: lin N: lin P: off N: lin P: sat N: sat P: lin N: sat P: sat A B D E C i i S D G G S D VDD VOUTVIN Lecture 27, Slide 4EECS40, Fall 2003 Prof. King Power Dissipation due to Direct-Path Current VDD-VT VT time vIN: i: Ipeak VDD 0 0 i S D G G S D VDD vOUTvIN peakDDscdp IVtE =Energy consumed per switching period: tsc 5 Lecture 27, Slide 9EECS40, Fall 2003 Prof. King CMOS NOR Gate A F B A B VDD 011 001 010 100 FBA Lecture 27, Slide 10EECS40, Fall 2003 Prof. King CMOS Pass Gate A X Y A Y = X if A 6 Lecture 27, Slide 11EECS40, Fall 2003 Prof. King VT is a function of VSB: The “Body Effect” ( )       = −++= i B F FSBFTT n N q kT VVV ln where 220 φ φφγ γ is the body effect coefficient When the body-source pn junction is reverse-biased, |VT| increases. Usually, we want to minimize γ so that IDsat will be the same for all transistors in a circuit. Lecture 27, Slide 12EECS40, Fall 2003 Prof. King Example (0.25µm CMOS technology) -2.5 -2 -1.5 -1 -0.5 0 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 V BS (V) V T (V )
Docsity logo



Copyright © 2024 Ladybird Srl - Via Leonardo da Vinci 16, 10126, Torino, Italy - VAT 10816460017 - All rights reserved