Field Effect Transistors - Engineering Circuit Analysis - Lecture Slides, Slides of Electrical Circuit Analysis

Download Field Effect Transistors - Engineering Circuit Analysis - Lecture Slides and more Slides Electrical Circuit Analysis in PDF only on Docsity! Engineering 43 FETs-1 (Field Effect Transistors) Docsity.com Learning Goals • Understand the Basic Physics of MOSFET Operation • Describe the Regions of Operation for a MOSFET Device • Use the Graphical LOAD-LINE method to analyze the operation of basic MOSFET Amplifiers • Determine the LARGE-SIGNAL Bias-Point (Q- Point) for MOSFET circuits Docsity.com The concept of voltage-controlled resistance • An independent Voltage Applied to the Control connection (the “Gate) regulates the flow of Current Thru the device Gate Drain (or Source) Source (or Drain) Docsity.com Flavors of FETS • Junction Field Effect Transistor → JFET – A Normally ON transistor • Reverse Biasing two PN Junctions will “Pinch Off” a Conducting Channel Docsity.com Flavors of FETS • Depletion Mode MOSFET – Another Normally ON transistor • Applying a Gate Voltage Drives Carriers OUT of the conducting Channel to turn off the transistor – No direct Gate↔Channel Connection • An Isulated Gate Field Effect Transistor (IGFET) Docsity.com Enhancement Mode - IGFET • Insulated Gate Field Effect Transistors are Normally-Off devices  Applying a Positive Voltage to the Gate will attract e− to the Channel • This will eventually “invert” a thin region below the gate to N-type, creating a conducting channel between S & D  IGFETs are Great Switches • Used in almost all digital IC’s  Back-to-Back PN Jcns Between “source” & “drain” Docsity.com MOSFET Nomenclature & Dims • We will consider only Enhancement FETs n+ ≡ Heavily Doped n-Type An n-Channel (nFET) enhancement mode FET Docsity.com MOSFET: Current & Speed • In General the performance of an Enhancement Mode MOSFET – Current Carrying Capacity Increases with Increasing Width, W – On/Off Switching Speed Increases with Decreasing Gate Length, L • As of 2011 the minimum (best) value for L was about 22 nm Docsity.com MOSFET Operation: CutOff • As seen in previous diagrams, unpowered MOSFETS have two OPOSING PN junctions – Channel→Source – Channel→Drain • With NO Potential applied to the gate No current can flow • From the Previous slide the Minimum Gate Voltage required for current-flow is called the “Threshold” Voltage, Vto or Vth • A MOSFET with VGS < Vth is “CutOff” – i.e.; The MOSFET is Off, and the Drain Current, iD = 0 Docsity.com MOSFET Circuit in CutOff • The Diagram at Right shows an nMOSFET in CutOff • For vGS<Vto the PN Jcn between the Drain & Body is Reversed Biased by vDS and NO Current flows – Vto is typically 0.5-5 Volts • Mathematically this is simple; in CutOff, the Drain Current toGSD Vvi ≤= for0 Docsity.com Power MOSFET Data Sheet Philips Semiconductors Product specification Philips Semiconductors Product specification Cel PowerMOS transistor IRF830 PowerMOS transistor IRF830 Avalanche energy rated Avalanche energy rated Ce FEATURES SYMBOL QUICK REFERENCE DATA THERMAL RESISTANCES + Repetitve Avalanche Rated . , SYMBOL] PARAMETER CONDITIONS MIN. | TYP. | MAX. | UNIT + Fast switching Voss = 500 V Ran Thermal resistance junction ~.- a tkw + High thermal cycling performance ee erountina bewe + Low thermal resistance lp=5.9A Raja | Thermal resistance junction |in tree air - |e] - |kw to ambient Rogow $15.2 . ELECTRICAL CHARACTERISTICS T= 25 ‘Cunless otherwise specified GENERAL DESCRIPTION PINNING SOT78 (TO220AB) SYMBOL |PARAMETER CONDITIONS MIN. | TYP. | MAX. | UNIT nna, enhancement med IN DESCRIPTION aS Vewwss [Drain source breakdown [Vaz =0V; 1 = 0.25 mA sof - | - | v ficld-cffect_ “power cistor, J intendedtor use in of-ine switched AVienoss /{ Drain source breakdown ~ Pot - | ere mode power, supplies, T.V. and 1 voltage ten iperat * Monitor power supplies, ic . Peete iment 3 |source vice" [Gate threshold voltage 20} 30 | 40] v switching applications. a tad |arain Toss Drain-source leakage current} - [a | 25 | ua ‘The IRF830_ is supplied in the 1 Ve - | 30 | 250 | ua SOT78 (TO220AB) conventional loss [Gate-source leakage current 10_| 200 paded package Quen, | Total gate charge ~ | 53 | es | nc a JGate-source charge 4 | 6 | nc LIMITING VALUES oud [Gate-drain (Miller) charge = | 28 | 34 | nc Limiting values in accordance wth the Absolute Maximum System (IEC 134) tues [Turm-on delay time ~Tao | | ns ‘SYMBOL [PARAMETER [CONDITIONS Min, [ MAX. | UNIT Y [Tum-on nse tme >|]: fs Voss [Drain-scurce voltage T= 25 °C to 150°C ~ ‘500 Vv om) um-off delay time 2 > | ts veg |Drain-gate = 25 °C to 150°C; Rog = 20 KO : 500 v f [Turn-off fall time 40 ns ve |Gate-Source voltage - £30 v Ly intemal drain inductance __ | Measured from tab to centre of die - [35 | - [nH hy Continuous drain current |T,. = - sg | A G Internal drain inductance | Measured from drain lead to centre ofdie | - | 45] - | nH Tro = 10 37 | A G Internal source inductance | Measured from source lead to source - [75] - | ow low Pulsed drain current t 24 A bond pad 8 Total dissipation Tro = iz | w < = = Tr Teg Operating junction and wo | °C Ces Input capacitance Ves = OV; Vos = 25 V; f= 1 MHZ - [eo] - | pe storage temperature range Coxe JOutput capacitance = [96] > | pF Ce Feedback capacitance - | 4 | - | oF AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance wth the Absolute Maximum System (IEC 134) SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS ‘SYMBOL [PARAMETER [CONDITIONS MIN. [| Max. | UNIT T= 25 ‘C unless otherwise specified Es INon-repetitive avalanche | Unclamped inductive load, |,, = 42 A 287 | md SYMBOL [PARAMETER CONDITIONS MIN. [ TYP. [MAX. [UNIT lenergy = 0.24 ms; T, prior to avalanche = 25°C; = ~T fc g0V Ra Eee aetor Ip Gontinaous source current SC 59] A Sq |Repetive vata energy a8 A = 2.5 ps, Tin 1 | om lon [ulsed source current (body Jo [mya refer to fig: ie C. Res = Vso [Diode forward voltage I, = 6A; Ve: - - 12 | Vv hs, and non-repetitive - 59 | A = = = 7 ~ taysanche and non peti & Reverse recovery te oe Is = 6 A; Ves = 0 V; di/dt = 100 Afus. : 390 : 3 Docsity.com nMOSFET in Triode Operation • When vGS > Vto a conducting channel forms below the gate Docsity.com Triode Operation • When vGS > Vto a conducting channel forms below the gate. – That is the “type” of the silicon is INVERTED from p-Type to n-Type • Thus this conducting Channel is often called an “Inversion Layer” • The greater vGS The more the conducting the channel becomes • The Channel resistance is a fcn of vGS Docsity.com Triode Operation • In the Triode Region, iD increases for – Increasing vGS – Increasing vDS • Thus current thru the device depends on the voltage at ALL three connections as long as vDS < (vGS − Vto) – The Three-Connection dependency is why this region is called TRIODE ( ) toGStoGSDS VvVvv ≥−< and Docsity.com PinchOff Illustrated • The layer is THICKEST at the Source and ZERO at the Drain when • Thus Have PinchOff when • At this Point the channel is WIDE and the Source-End, and Zero- width at the Drain End → ( ) toDSGS tochanGS Vvv VLvv =− =− or GStoDS vVv ≥+ Pinched Off at Drain Docsity.com TriOde Region Summarized • vDS ≤ (vGS − Vto) → iD = f(vDS , VGS) Start of TriOde → Channel Formation Finish of TriOde → Drain PinchOff Docsity.com PinchOff  iD Saturation • As vDS increases the “PinchOff Point”, xpop, Moves BACKWARDS towards the Source • Once the channel Pinches Off, the drain current, iD, NO Longer increases with increasing vDS • In other words, for a given vGS, the Current “Saturates” (stays constant) After PinchOff as shown below Docsity.com Operation in Saturation • Notice that in SAT iD varies with vGS – Note that vDS does NOT appear in this Equation – vDS (on vi curve) does NOT affect iD after Channel-PinchOff – In SAT a MOSFET is true 3- terminal device; current depends ONLY on the CONTROL Signal, vGS ( )2toGSD VvKi −= Docsity.com Saturation Summarized • vDS ≥ (vGS − Vto) → iD ≠ f(vDS) PinchOff Moved BACK from Drain Docsity.com Triode↔Saturation Boundary • At the boundary Line the nMOSFET just Barely Pinches Off at the Drain end thus: • By KVL • Substituting Find • Or at the Boundary • Sub for vGS into iD,sat Eqn toGD Vv = Boundary Line DSGSGD vvv −= toDSGSGD Vvvv =−= toDSGS Vvv += [ ]( ) [ ]( )2 2 totoDSD toGSD VVvKi VvKi −+= −= Docsity.com The completed Plot 0 1 2 3 4 5 6 7 8 9 10 0 5 10 15 20 25 30 35 vDS (Volts) iD (m A ) nMOSFET vi Curve - Ex 12.1 VGS<Vto vGS=3V vGS=4V vGS=5V vGS=6V Docsity.com MATLAB Code-1 % Bruce Mayer, PE % ENGR43 * 14Jan12 % file = nMOSFET_Plot_ex12_1_1201.m W = 160; % µm L = 2; % µm KP = 50; % µA/sq-V Vto = 2' % V % % calc Parameter K K = (W/L)*KP/2; % µA/sqV) % % set vGS values that exceed CutOff at 2V vGS = [3, 4, 5, 6]; % % calc boundary Triode/Sat boundary by finding iD at the START of sat % region iDsat_uA = K*(vGS-Vto).^2; % in µA iDsat_mA = iDsat_uA/1000 % % show cutoff line vDSco = linspace(0,10, 200); iDco = zeros(200); % DeBug Command => plot(vDSco, iDco, 'LineWidth', 3) % % Calc iD in Triode Region for vGS>Vto (Pinched off at Drain) %* use eqn (12.6) in text vDSsat = sqrt(iDsat_uA/K) % must take care with units % plot(vDSsat,iDsat_mA, '--*', 'LineWidth', 3), grid, xlabel('vDSsat'), ylabel('iDsat') disp('showing Triode-Sat Boundary - Hit any key to continue') pause % Docsity.com MATLAB Code-2 % then iD in triode region vDSt1 = linspace(0, vDSsat(1)); % V vDSt2 = linspace(0, vDSsat(2)) vDSt3 = linspace(0, vDSsat(3)) vDSt4 = linspace(0, vDSsat(4)) iDt1_mA = K*(2*(vGS(1)-Vto)*vDSt1-vDSt1.^2)/1000; % mA iDt2_mA = K*(2*(vGS(2)-Vto)*vDSt2-vDSt2.^2)/1000; % mA iDt3_mA = K*(2*(vGS(3)-Vto)*vDSt3-vDSt3.^2)/1000; % mA iDt4_mA = K*(2*(vGS(4)-Vto)*vDSt4-vDSt4.^2)/1000; % mA % % % DeBug Command =>plot(vDSt1,iDt1_mA, vDSt4,iDt4_mA) % % use TwoPoint Plots in Sat iDsat1 =[iDsat_mA(1),iDsat_mA(1)] iDsat2 =[iDsat_mA(2),iDsat_mA(2)] iDsat3 =[iDsat_mA(3),iDsat_mA(3)] iDsat4 =[iDsat_mA(4),iDsat_mA(4)] vDSsat1 = [vDSsat(1), 10] vDSsat2 = [vDSsat(2), 10] vDSsat3 = [vDSsat(3), 10] vDSsat4 = [vDSsat(4), 10] % Docsity.com