Download Final Exam Solutions - First-Year Interest Group Seminar | N 1 and more Exams Health sciences in PDF only on Docsity! EE345M Final Exam Solution Fall 2001 Page 1 Jonathan W. Valvano (20) Question 1. Here is one possible analog circuit that satisfies the specifications: +2.5 10kΩ10kΩ 10kΩ10kΩ +12V -12V 0.1µF AD620 0.1µF R = = 1kΩ G 49.4kΩ 50-1 REF43 +12V 0.1µF V1 V2 3V =50(V -V )21 OP07 (20) Question 2. Consider a 128K by 8 bit static RAM interface. Part a) Draw a combined read timing diagram assuming no cycle stretching. Address R/W D7-D0 RDA E 0 125 60 60CSD 10 20 20 30 0 D7-D0 60 RDR RDA=(95,135) RDR=(95,125) ta =35 ta =35 =0 Part b) If ta is 35 ns, then RDA just overlaps RDR. (20) Question 3. Conversions from real variables to fixed-point versions. Overflow will be handled by promotion to 32-bits, performing the controller in 32-bit math, then performing a ceiling/floor operation before demotion. xstar = 100•X* x(n) = 100•X(t) u(n) = 1000•V(t) e(n) = xstar - x(n) EE345M Final Exam Solution Fall 2001 Page 2 proportional term Vp(t) = 0.0512•e(t) original proportional term up(n) = 1000•0.0512•e(t) convert Vp to up up(n) = 1000•0.0512•e(n)/100 convert e(t) to e(n) up(n) = (512•e(n))/1000 make it fixed-point up(n) = (64•e(n))/125 simplify integral term Vi(t) = 0.0408•∫e(τ)dτ original integral term Vi(t) = 0.0408•∑e(τ)∆t approximate integration with sum ui(n) = 1000•0.0408•∑e(τ)∆t convert Vi to ui ui(n) = 1000•0.0408•∑e(n)∆t/100 convert e(t) to e(n) ui(n) = 0.0408•∑e(n) simplify, ∆t = 0.1s ui(n) = ui(n-1)+0.0408•e(n) simplify sum ui(n) = ui(n-1)+408•e(n)/10000 make it fixed-point ui(n) = ui(n-1)+51•e(n)/1250 simplify put together u(n) = up(n) + ui(n) (10) Question 4. If the FIFO is big enough, then the system will run continuously if the sum of the average execution times is less than 1/fs. In particular, the FIFO will not overflow. The system will be real-time if the main program runs with interrupts enabled, and the other ISRs have short and bounded execution times. So 1/fs > Adin+Fifo_Put+Fifo_Get+Process=(25+15+20+1000) = 1060 µsec so fs < 943 Hz (10) Question 5. First, write $15BCD in binary 0001,0101,1011,1100,1101. The offset is the bottom 14 bits 01,1011,1100,1101 = $1BCD. The memory address is $8000+offset =$9BCD. The program page number is the rest = 000101 = $05 PPAGE = 0x05; data = *((char *)(0x9BCD)); Part b) Again, write $15BCD in binary 0001,0101,1011,1100,1101. The offset is the bottom 12 bits 1011,1100,1101 = $0BCD. The memory address is $7000+offset =$7BCD. The data page number is the rest = 00010101 = $15 DPAGE = 0x15; data = *((char *)(0x7BCD)); Part c) The two have separate windows. The data page window is $7000-$7FFF and program page window is $8000-$BFFF. The RAM uses CSD and the ROM uses CSP0. So when 0x9BCD is accessed CSP0 is active. When 0x7BCD is accessed CSD is active.