Download Final Exam with Answer Key for Advanced VLSI Design and Applications | ECEN 6263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 6263
Fall 2000
Final
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All questions must be answered on test paper!
Open Book, Open Notes
1, In the circuit below, the C2 > C| and.C, > C3 so that the delay of any signal passing
through V2 is very long. Estimate the delays in the circuit below using the RC model
developed in class including the effects of the transistor threshold voltages V7, and Vip
Use as parameters the channel resistances of the six transistors, Rj, ..., Rg and the node
capacitances, C}, ...,C3. You may assume that the capacitances already contain ail par-
asitics from the transistors and interconnect. :
M3 V3
rs c V2 ous
Lo
— | [as Fe,
Mi
V1 Note: it is not rec-
, IZ ommended to use
My C 1 a pFET pulldown!
a. Sketch the voltage waveforms for V2 and V3 when V1 is as shown below. Show the
¢ value of the voltages in the diagram. Assume that V1(t) = 0 for t<0. Hint: there isa
glitch on V3 and you can assume that it is a full swing glitch because of the long
delay at V2.
Vi
Vdd Gnd
t
V2.
| wa es
t
V3 p= VIL,
Gans L\ end '
ECEN 6263 Fall 2000 Final December 13, 2000 page 1 of6
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b:: What is the:delay from-V1 to. V2-when V1 goes from low to high?
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S c.What is the delay from ‘V1 t0.V3"when VI goes from:tow to high (after the glitch if
any dies out)? . :
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< d. What is the delay from V1 to V2 when V1 goes from high to iow?
e. What is the delay from V1 to V3 when V1 goes from high to low (after the glitch if
any dies out)?
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ECEN 6263 Fall 2060 Finat Dedember 13, 2000 page 2 of 6
3. The notes-show the look ahead carry tree for an 8 bit adder.
gd a. How would the tree diagram be extended for 2" bit adder? Show how many rows and
{ columns there would be.
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b. The CPL and CVSL gates have-been proposed for implementing the carry save adder
tree ina multiplier. - Would they be appropriate to implement the look ahead adder
}v tree also? Explain why or why not for full credit.
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ECEN 6263 Fall 2006 Finai December 13, 2000 page'S of 6
4. Draw a transistor diagram (not layout or stick diagram) for a logic gate which impie-
ments AB+AC+BC, AB+AC+BC. Make sure that common circuitry is shared between
the two gates.
a. AsaCVSL gate.
(0 Sen ed anlat ne a
b. As a CPL gate.
[0 Ge Cher naiod a ne
ECEN 6263 Fali 2000 Final December 13, 2000 page 6 of 6
