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Final Examination with Resolution - Digital VLSI Design Systems | ECEN 5263, Exams of Electrical and Electronics Engineering

Oklahoma State University (OSU) - Stillwater Electrical and Electronics Engineering

Prof. Louis Johnson

Material Type: Exam; Professor: Johnson; Class: VLSI DIGITAL SYS DES; Subject: Electrical and Computer Engineering ; University: Oklahoma State University - Stillwater; Term: Spring 2010;

Typology: Exams

2010/2011

Uploaded on 07/17/2011

koofers-user-ngv 🇺🇸

10 documents

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Download Final Examination with Resolution - Digital VLSI Design Systems | ECEN 5263 and more Exams Electrical and Electronics Engineering in PDF only on Docsity! ECEN 5263 Spring 2010 Final Exam WRITE YOUR NAME HERE A NSly ef All questions must be answered on test paper! Open Book, Open Notes I. Ifthe transistor below is fabricated in a process with a channel sheet resistance, R, = 10KQ, find the total channel resistance. Show your reasoning for full credit. R= TORR | eT KIe wes ECEN 5263 Spring 2010 Final Exam May 3,2010 page | of 4 2. An efficient CVSL circuit for XOR/XNOR is shown below. ¢> b. Draw a transistor level diagranfor a dual-rail partial swing pass transistor logic (CPL with keepers) KOR/XNOR gate. ECEN 5263 Spring 2010 Final Exam May 3,2010 page 2 of 4

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Final Examination with Resolution - Digital VLSI Design Systems | ECEN 5263, Exams of Electrical and Electronics Engineering

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