Download Understanding D-Flip Flops: Structure, Analysis, and Applications and more Exams Electrical and Electronics Engineering in PDF only on Docsity! 1 Copyright © 2007 Elsevier Digital Logic Design What is a D-Flip Flop James E. Stine Copyright © 2007 Elsevier Introduction • Outputs of sequential logic depend on current and prior input values. • Sequential logic thus has memory. • Some definitions: – State: contains all the information about a circuit necessary to explain its future behavior – Latches and flip-flops: state elements that store one bit of state – Synchronous sequential circuits: combinational logic followed by a bank of flip-flops Finite State Machines and testing • FSM designs are hard to test! – Why? • They hard to test because we need to use flip-flops to store the state *AND* the outputs. • So, let’s suppose I have 3 bits for encoding state and 6 bits for the output (just like our tbird example), how many vectors would I need to test to make it sure it works perfectly? Copyright © 2007 Elsevier € 2#bits / state+#bits / output = 23+6 = 29 = 512 vectors Copyright © 2007 Elsevier Sequential Circuits • give sequence to events • have memory (short-term) • use feedback from output to input to store information • But, what do they look like inside? D-Flip Flops • We have been calling the device that stores bits a DFF or D-Flip Flop. • But, what’s inside this thing? – How does it only work on an edge? – What is a reset or clear? • And, is there any other device that stores information? Copyright © 2007 Elsevier Copyright © 2007 Elsevier State Elements • The state of a circuit determines its future behavior • Some other state elements that store state or information – Bistable circuit – SR Latch – D Latch – D Flip-flop 2 Copyright © 2007 Elsevier Bistable Circuit • Fundamental building block of other state elements • Two outputs: Q, Q • No inputs BTW, this is what memory looks like inside your computer!! Copyright © 2007 Elsevier Bistable Circuit Analysis • Consider the two possible cases: – Q = 0: then Q = 1 and Q = 0 (consistent) – Q = 1: then Q = 0 and Q = 1 (consistent) • Bistable circuit stores 1 bit of state in the state variable, Q (or Q ) • But there are no inputs to control the state – boo hoo. Notice the values always work out – that is, you don’t have conflicting values = stable!!! Copyright © 2007 Elsevier SR Latch • Let’s add those input and have one Set the input and the other Reset it. • Set/Reset Latch (SR Latch) • Definitions – Set: Make the output 1 – Reset: Make the output 0 • When the set input, S, is 1 (and R = 0), Q is set to 1 • When the reset input, R, is 1 (and S = 0), Q is reset to 0 Notice : more logic means more functionality as with the adder discussion! Feedback elements make modeling hard for HDL! Complexity D el ay (c os t) NRE : non-recurring engineering cost Copyright © 2007 Elsevier SR Latch Analysis • Let’s try all possibilities at the input! • 2 inputs means 4 possibilities. • Consider the four possible cases: – S = 1, R = 0 – S = 0, R = 1 – S = 0, R = 0 – S = 1, R = 1 Copyright © 2007 Elsevier SR Latch Analysis – S = 1, R = 0: then Q = 1 and Q = 0 – S = 0, R = 1: then Q = 0 and Q = 1 Copyright © 2007 Elsevier SR Latch Analysis – S = 0, R = 0: then Q = Qprev and Q = Qprev (memory!) – S = 1, R = 1: then Q = 0 and Q = 0 (invalid state: Q ≠ NOT Q) Important: Device still works, but engineers do not like that Q and Q_bar are the same, which is contradicting to its operation!
