Download Flip-Flops Conversion: Designing JK Flip-Flops using SR Flip-Flops and Combinational Logic and more Slides Digital Systems Design in PDF only on Docsity! Flip-Flops Conversion • Implement a JK flip-flop with a SR flip-flop and a minimal AND-OR-NOT network. S R Q Q’ Combinational logic J K JK flip-flop Solve the combinational logic design problem S = f1(J, K, Q) R = f2(J, K, Q) Docsity.com Flip-Flops Conversion • How to attain the specification of the combinational circuit? S R Q Q’ 0 0 Qprev Q’prev 0 1 0 1 1 0 1 0 1 1 J K Q Q’ 0 0 Qprev Q’prev 0 1 0 1 1 0 1 0 1 1 Q’prev Qprev S = f1(J, K, Q) R = f2(J, K, Q) J K Qprev Q S R 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 Truth table for combinational logic 0 x x 0 x 0 0 x 0 1 1 0 1 0 0 1 Docsity.com Sequential Circuit Design • Design the system with two JK flip-flops and a minimal AND- OR-NOT network. X Q1(t) Q0(t) Q1(t+1) Q0(t+1) J1 K1 J0 K0 y 0 0 0 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 0 1 1 1 1 1 1 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 0 1 1 1 0 1 1 0 X 1 X x 1 x 0 1 X 0 X x 0 x 1 0 X x 1 1 X x 0 0 X x 0 0 X x 0 Docsity.com Sequential Circuit Design X Q1(t) Q0(t) J1 K1 J0 K0 y 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 0 1 1 1 1 0 X 1 X x 1 x 0 1 X 0 X x 0 x 1 0 X x 1 1 X x 0 0 X x 0 0 X x 0 x x 0 1 x x 1 0 00 01 11 10 0 1 Q1Q0 X Kmap for J1 J1 = X’Q0+XQ0’ 0 1 x x 1 0 x x 00 01 11 10 0 1 Q1Q0 X Kmap for K1 K1 = X’ Q0’+X Q0 0 x x 0 1 x x 0 00 01 11 10 0 1 Q1Q0 X Kmap for J0 x 0 0 x x 0 1 x 00 01 11 10 0 1 Q1Q0 X Kmap for K0 J0 = X’Q1 K0 = X’ Q1’ 0 1 1 1 0 1 1 1 00 01 11 10 0 1 Q1Q0 X Kmap for y y = Q1’+Q0 Docsity.com Timing • Circuit implemented using two T flip-flops and a D flip-flop. • Timing characteristics: – T flip-flop: • clock-to-Q maximum delay tpcq = 2ns • clock-to-Q minimum delay tccq = 1.8ns • setup time tsetup = 1ns • hold time thold = 1.5ns – D flip-flop: • clock-to-Q maximum delay tpcq = 2.5ns • clock-to-Q minimum delay tccq = 2.3ns • setup time tsetup = 2.5ns • hold time thold = 2ns – NAND gate: • propagation delay tpd = 1ns • contamination delay tcd = 0.8ns – Inverter: • propagation delay tpd = 0.5ns • contamination delay tcd = 0.3ns Docsity.com Timing • What is the maximum clock frequency of this circuit? P1: tpcq(D) + tpd(NAND) + tsetup(T) <= clock cycle P2: tpcq(T) + tpd(NOT) + tsetup(D) <= clock cycle P3: tpcq(T) + tpd(NAND) + tsetup(T) <= clock cycle 2.5 + 1 + 1 <= clock cycle 2 + 0.5 + 2.5 <= clock cycle 2 + 1 + 1 <= clock cycle Min cycle = 5 ns max f = 1 / min cycle = 200 MHz Docsity.com Timing • what is the maximum clock skew that the circuit can tolerate before it might experience a hold time violation? P1: tccq(D) + tcd(NAND) >= thold(T) + skew P2: tccq(T) + tcd(NOT) >= thold(D) + skew P3: tccq(T) + tcd(NAND) >= thold(T) + skew 2.3 + 0.8 >= 1.5 + skew 1.8 + 0.3 >= 2 + skew 1.8 + 0.8 >= 1.5 + skew Max skew = 0.1ns Docsity.com Decoder & MUX • three-input Boolean function f(a, b, c) = ∑Pm(1, 2, 4, 7) + ∑ Pd(3) 0 1 x 1 1 0 1 0 00 01 11 10 0 1 ab c f = a’b’c + a'bc’ + abc + ab’c’ + (a’b’c) Docsity.com
