Flip Flops: Understanding Edge-Triggered and Level-Sensitive Latch and Flip-Flop Circuits, Slides of Digital Logic Design and Programming

Download Flip Flops: Understanding Edge-Triggered and Level-Sensitive Latch and Flip-Flop Circuits and more Slides Digital Logic Design and Programming in PDF only on Docsity! Flip Flops Not a gymnastic movement. Docsity.com Class 20 – Flip Flops • Definitions • Latches – Set-Reset – SR – The D Latch • Material from section 5-3 of text Docsity.com Master Slave Flip-flops • The Master-Slave SR Flip-flop • And its operation Docsity.com Master Slave D Flip-flop • Can be constructed from the MS SR FF by replacing the master SR latch by a D latch. • This arrangement is also negative edge triggered. Docsity.com A HDL model of the same • The SR latch model with control input C ENTITY SR_latch IS PORT (S,R,C : IN BIT; Q, Q_bar : OUT BIT); END SR_latch; ARCHITECTURE one OF SR_latch IS SIGNAL CS,CR : BIT; SIGNAL Q_int, Q_bar_int : BIT; BEGIN CS <= S nand C after 1 ns; CR <= R nand C after 1 ns; Q_int <= CS nand Q_bar_int after 1 ns; Q_bar_int <= CR nand Q_int after 1 ns; Q <= Q_int; Q_bar <= Q_bar_int; END one; Docsity.com The D Flip-flop • The D can be constructed from the use of a D latch and an SR latch. Docsity.com For a positive edge FF • Add an inverter to the clock input Docsity.com HDL model and simulation • A HDL model of the D latch was written. ENTITY dlatch IS PORT (D,C : IN BIT; Q,Q_BAR : OUT BIT); END dlatch; ARCHITECTURE one OF dlatch IS SIGNAL S_bar, R_bar, D_bar : BIT; SIGNAL Q_int, Q_bar_int : BIT; BEGIN S_bar <= D nand C after 1 ns; R_bar <= D_bar nand C after 1 ns; D_bar <= not D after 1 ns; Q_int <= S_bar nand Q_bar_int after 1 ns; Q_bar_int <= R_bar nand Q_int after 1 ns; Q <= Q_int; Q_BAR <= Q_bar_int; END one; Docsity.com