Understanding NAND Latch and J-K Flip-Flops in Digital Electronics - Prof. Andrew Fagg, Assignments of Aerospace Engineering

Download Understanding NAND Latch and J-K Flip-Flops in Digital Electronics - Prof. Andrew Fagg and more Assignments Aerospace Engineering in PDF only on Docsity! Last Time • Flip-flops • Combining flip-flops with combinatorial logic • Counter design Today • A bit more on flip-flops • Memory • Microcontroller essentials NAND Latch Consider this initial state Is this a stable state? 1 0 1 1 Yes! NAND Latch What happens with S is set to 0? 0 0->? 1 1->? NAND Latch What happens with S is set to 0? Q becomes 1 (thus S ‘sets’ Q) 0 0->1 1 1->0 NAND Latch Now set R to 0 – what happens? 1 1->? 0 0->? NAND Latch Now set R to 0 – what happens? The state flips back (Q is ‘reset’) 1 1->0 0 0->1 NAND Latch Finally: set R to 1 – what happens? 1 0->? 1 1->? Timing Diagram Representation S R Q Q’ Note small delay in response in Q and Q’ Timing Diagram Representation S R Q Q’ When S returns to high – both Q and Q’ remain in the same state Timing Diagram Representation S R Q Q’ ? Timing Diagram Representation S R Q Q’ No change in Q and Q’ J-K Flip-Flops wnC)— — © 1 —C)7 J-K Flip-Flops No matter what the clock state is: • S (set): when low, forces Q to 1 • R (reset): when low, forces Q to 0 In general, these are both high Memory What are the essential components of a memory? A Memory Abstraction • We think of memory as an array of elements – each with its own address • Each element contains a value • It is most common for the values to by 8- bits wide (so a byte) Memory Operations Read foo(A+5); reads the value from the memory location referenced by ‘A’ and adds the value to 5. The result is handed to a function called foo(); Types of Memory • Read Only Memory (ROM) – Computer cannot arbitrarily change state of this memory – When power is lost, the contents are maintained Types of Memory Erasable/Programmable ROM (EPROM) • State can be changed under very specific conditions (usually not when connected to a comptuer) • Our microcontrollers have an Electrically Erasable/Programmable ROM (EEPROM) for program storage Last Time • R-S Latch (the heart of our flip flops) • J-K flip flops • Memory: abstraction and types Project Grading • Personal report: assign percent effort to each group member (including yourself) • The group receives a grade of G • Person i gives person k an effort score of (percent) • Person k receives the following grade:
i kigG ,* kig , Example: A Read/Write Memory Module Inputs: • 2 Address bits: A0 and A1 • 1 “chip select” (CS) bit • 1 read/write bit (1 = read; 0 = write) • 1 clock signal (CLK) Input or Output: • Data bit (connected to the “data bus”) Implementing A Read/Write Memory Module With 2 address bits, how many memory elements can we address? How could we implement each memory element? Memory Module Specification When chip select is low: • No memory elements change state • The memory does not drive the data bus Memory Module Specification When chip select is high: • If R/W is high: – Drive the data bus with the value that is stored in the element specified by A1, A0 • If R/W is low: – Store the value that is on the data bus in the element specified by A1, A0 Memory Timing Diagram Q2 A1 A0 R/W CS CLK D Memory Timing Diagram Q2 A1 A0 R/W CS CLK D What happens next? Memory Timing Diagram Q2 A1 A0 R/W CS CLK D Chip is selected Memory Timing Diagram Q2 A1 A0 R/W CS CLK D Address memory element 2 Memory Timing Diagram Q2 A1 A0 R/W CS CLK D Memory element 2 changes state to low Memory Timing Diagram Q2 A1 A0 R/W CS CLK D Setup time: all inputs must be valid during this time Memory Timing Diagram Q2 A1 A0 R/W CS CLK D Hold time: all inputs must continue to be valid Memory Timing Diagram II Q2 A1 A0 R/W CS CLK D What happens next? Memory Timing Diagram II Q2 A1 A0 R/W CS CLK D On chip select – drive data bus from Q2 Memory Timing Diagram II Q2 A1 A0 R/W CS CLK D What happens now? Components of a Microprocessor • Registers (fast-access memory) – General purpose: used for data storage – Special purpose: used to control the behavior of the microprocessor and/or the devices connected to it • Instruction decoder – Instructions are the primitive “actions” that the microprocessor can perform – Load/store to/from memory, AND, ADD, JUMP, TEST, … Components of a Microprocessor • Arithmetic Logical Unit (ALU) • Memory control logic • Timers – Including timing mechanisms for instruction fetch and execution • Interrupt processor Instruction Fetch/Execution Cycle • While one instruction is being executed, the next is already being fetched from memory • In many cases: each step happens on a single clock cycle From Atmel Mega8 spec Instruction Execution Cycle Result stored in destination register Status register state changed Data Bus 8-bit An Example: the Atmel Mega8& < { Program Status pieen +— Counter i“) and Control rogram Memory bq] t | 32 x8 Instruction General Register Purpose f+——__ Registrers Instruction Decoder os D e | = a B 2 3 o 2 3 Control Lines 3 3 < a a 6 S ® a = = 3 a = J J EEPROM 1/0 Lines Interrupt Unit SPI Unit Watchdog Timer Analog Comparator iO Module1 i/O Module 2 i/O Module n Atmel Mega8 8-bit data bus • Primary mechanism for data exchange Random Access Memory (RAM) • 1 KByte in size Atmel Mega8 Random Access Memory (RAM) • 1 KByte in size Note: in high-end processors, RAM is a separate component Atmel Mega8 Flash (EEPROM) • Program storage • 8 KByte in size Atmel Mega8 Arithmetic Logical Unit • Data inputs from registers • Control inputs not shown (derived from instruction decoder) Atmel Mega8 Machine-Level Programs Machine-level programs are stored as sequences of machine instructions • Stored in program memory • Execution is generally sequential (instructions are executed in order) • But – with occasional “jumps” to other locations in memory Types of Instructions • Memory operations: transfer data values between memory and the internal registers • Mathematical operations: ADD, SUBTRACT, MULT, AND, etc. • Tests: value == 0, value > 0, etc. • Program flow: jump to a new location, jump conditionally (e.g., if the last test was true) Instruction decoder • Translates current instruction into control signals for the rest of the processor Atmel Mega8 Status register • Many machine instructions affect the state of this register Atmel Mega8 Mega8 Status Register Interrupt enable • If ‘1’, the currently executing program can be interrupted by another event (e.g., a byte arriving through the serial port) Mega8 Status Register Negative flag • Set if an arithmetic operation resulted in a negative value Mega8 Status Register Zero flag • Set if an arithmetic operation resulted in a value of zero Mega8 Status Register Carry flag • Set if an arithmetic operation resulted in a carry (with an unsigned value)